Cores
Open HDL cores for FPGA. License, tests and activity checked on GitHub.
| Core | Maturity | License | Language | Activity |
|---|---|---|---|---|
| Amaranth HDL Generators and frameworks | M4 · Production-ready | BSD-2-Clause | — | updated 14 days ago |
| AccelFury core-template Generators and frameworks | M2 · Simulation-tested | CERN-OHL-S-2.0 + AGPL + CC-BY-SA | Rust/SystemVerilog/TypeScript | updated 5 months ago |
| LiteX Generators and frameworks | M4 · Production-ready | M6 | Migen/Python/Verilog | updated 8 days ago |