Cores
Open HDL cores for FPGA. License, tests and activity checked on GitHub.
| Core | Maturity | License | Language | Activity |
|---|---|---|---|---|
| IObundle cache Memory and storage | M1 · Prototype | CERN-OHL-S-2.0 | — | updated 11 days ago |
| LiteDRAM Memory and storage | M2 · Simulation-tested | No license found | Migen/Python/Verilog | updated 8 days ago |
| LiteSATA Memory and storage | M2 · Simulation-tested | No license found | Migen/Python/Verilog | updated 8 days ago |
| LiteSDCard Memory and storage | M2 · Simulation-tested | No license found | Migen/Python/Verilog | updated 8 days ago |
| fifo Memory and storage | M2 · Simulation-tested | No license found | — | updated 6 years ago |
| wb_ram Memory and storage | M1 · Prototype | No license found | — | — |
| LiteHyperBus Memory and storage | M1 · Prototype | No license found | — | — |
| opencores ddr controller Memory and storage | M1 · Prototype | No license found | Verilog/VHDL unknown until review | — |
| opencores sdram controller Memory and storage | M1 · Prototype | No license found | Verilog/VHDL unknown until review | — |