IObundle cache
Checked on GitHubOpen cache candidate.
Memory and storageCERN-OHL-S-2.0M1 · Prototypeupdated 11 days ago
Cores
Open HDL cores for FPGA. License, tests and activity checked on GitHub.
LiteDRAM
Checked on GitHubOpen DRAM controller ecosystem used with LiteX.
Memory and storageMigen/Python/VerilogNo license foundM2 · Simulation-testedupdated 8 days ago
LiteSATA
Checked on GitHubHigh-value storage/networked design reference.
Memory and storageMigen/Python/VerilogNo license foundM2 · Simulation-testedupdated 8 days ago
LiteSDCard
Checked on GitHubUseful storage peripheral for SoC designs.
Memory and storageMigen/Python/VerilogNo license foundM2 · Simulation-testedupdated 8 days ago
fifo
Checked on GitHubGeneric FIFO baseline.
Memory and storageNo license foundM2 · Simulation-testedupdated 6 years ago
Minimal SoC building block.
Memory and storageNo license foundM1 · Prototype
HyperRAM/HyperFlash ecosystem core.
Memory and storageNo license foundM1 · Prototype
DDR risk-model example.
Memory and storageVerilog/VHDL unknown until reviewNo license foundM1 · Prototype
Memory controller comparison.
Memory and storageVerilog/VHDL unknown until reviewNo license foundM1 · Prototype