Cores
Open HDL cores for FPGA. License, tests and activity checked on GitHub.
| Core | Maturity | License | Language | Activity |
|---|---|---|---|---|
| CORE-V-VERIF Verification and debug | M4 · Production-ready | No license found | SystemVerilog/UVM | updated 18 days ago |
| OpenCores WBScope Verification and debug | M1 · Prototype | GPL | Verilog | — |
| LiteScope Verification and debug | M2 · Simulation-tested | No license found | Migen/Python/Verilog | updated 8 days ago |
| wb_bfm Verification and debug | M2 · Simulation-tested | No license found | — | updated 9 years ago |