Cores

Open HDL cores for FPGA. License, tests and activity checked on GitHub.

4 results

CORE-V-VERIF

Checked on GitHub

Verification evidence model for CORE-V cores.

Verification and debugSystemVerilog/UVMNo license foundM4 · Production-readyupdated 18 days ago

Useful Wishbone-accessible debug core by ZipCPU author.

Verification and debugVerilogGPLM1 · Prototype

Checked on GitHub

Debug infrastructure for composition planner.

Verification and debugMigen/Python/VerilogNo license foundM2 · Simulation-testedupdated 8 days ago

Checked on GitHub

Verification helper for Wishbone cores.

Verification and debugNo license foundM2 · Simulation-testedupdated 9 years ago