Cores
Open HDL cores for FPGA. License, tests and activity checked on GitHub.
| Core | Maturity | License | Language | Activity |
|---|---|---|---|---|
| OpenCores Ethernet MAC Interfaces and peripherals | M1 · Prototype | No license found | Verilog | — |
| OpenCores I2C controller Interfaces and peripherals | M1 · Prototype | No license found | Verilog | — |
| OpenCores SPI master/slave Interfaces and peripherals | M1 · Prototype | No license found | Verilog | — |
| opencores aes core Cryptography | M1 · Prototype | No license found | Verilog/VHDL unknown until review | — |
| opencores can core Interfaces and peripherals | M1 · Prototype | No license found | Verilog/VHDL unknown until review | — |
| opencores ddr controller Memory and storage | M1 · Prototype | No license found | Verilog/VHDL unknown until review | — |
| opencores minsoc CPUs and compute | M1 · Prototype | No license found | Verilog/VHDL unknown until review | — |
| opencores sdram controller Memory and storage | M1 · Prototype | No license found | Verilog/VHDL unknown until review | — |
| opencores usbhostslave Interfaces and peripherals | M1 · Prototype | No license found | Verilog/VHDL unknown until review | — |
| opencores vga lcd Audio and video | M1 · Prototype | No license found | Verilog/VHDL unknown until review | — |