Important comparison point for LiteEth and IObundle Ethernet.
Interfaces and peripheralsVerilogNo license foundM1 · Prototype
Cores
Open HDL cores for FPGA. License, tests and activity checked on GitHub.
Common small peripheral for beginner/professional comparison.
Interfaces and peripheralsVerilogNo license foundM1 · Prototype
Common reusable peripheral baseline.
Interfaces and peripheralsVerilogNo license foundM1 · Prototype
Historical AES core to compare with OpenTitan AES.
CryptographyVerilog/VHDL unknown until reviewNo license foundM1 · Prototype
CAN/LIN category seed.
Interfaces and peripheralsVerilog/VHDL unknown until reviewNo license foundM1 · Prototype
DDR risk-model example.
Memory and storageVerilog/VHDL unknown until reviewNo license foundM1 · Prototype
Historical SoC integration reference.
CPUs and computeVerilog/VHDL unknown until reviewNo license foundM1 · Prototype
Memory controller comparison.
Memory and storageVerilog/VHDL unknown until reviewNo license foundM1 · Prototype
USB category seed.
Interfaces and peripheralsVerilog/VHDL unknown until reviewNo license foundM1 · Prototype
Video category seed.
Audio and videoVerilog/VHDL unknown until reviewNo license foundM1 · Prototype