P0confidence 2/5
OpenTitan IP blocks
High-quality IP block library with docs and verification culture.
Manual review is required.
Cores catalog
FPGA/ASIC/HDL/IP cores
An evidence-first catalog for fast engineering triage: reusable value, license risk, verification depth, and board fit before you open the upstream repo.
How to read cardsA card does not replace upstream docs or license review. Check warnings and commercial-use clarity first, then tests, board evidence, and toolchain fit.Why no featured vendor laneRanking is driven by evidence, review status, and reusable signals. Namespace or vendor identity does not create a privileged lane.
Cores124
P0 launch52
Needs review122
Open flow4
Board linked2
High-risk records in the current index
Submit evidenceP0confidence 2/5
Ibex
Small open RISC-V CPU used by OpenTitan.
Manual review is required.
P0confidence 2/5
LiteX
Central open SoC builder and integration framework.
Manual review is required.
P0confidence 2/5
OpenCores Wishbone
Bus protocol reference for OpenCores-era reusable IP.
Manual review is required.
P0confidence 2/5
OpenCores WBScope
Useful Wishbone-accessible debug core by ZipCPU author.
Manual review is required.
Catalog
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.
OpenCores Wishbone
bus/Wishbone
Manual review is required.
Bus protocol reference for OpenCores-era reusable IP.
Licensepublic-domain-like per OpenCores WISHBONE pageLicense riskpublic-domain-like per OpenCores WISHBONE page: HDL/docs/tests/examples still need manual review.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q54
Use54
Int52
Ver18
Specificationpublic-domain-like per OpenCores WISHBONE pageunknownWishbone
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.
OpenCores WBScope
verification/logic analyzer
Manual review is required.
Useful Wishbone-accessible debug core by ZipCPU author.
LicenseGPLLicense riskGPL: HDL/docs/tests/examples still need manual review.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q54
Use72
Int52
Ver40
VerilogGPLJTAG/debugWishbone
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.
OpenCores UART16550
peripheral/UART
The license requires manual review.
The source appears stale or legacy.
Canonical UART reference and common FuseSoC adaptations.
Licenseunknown until checkedLicense riskunknown until checked: HDL/docs/tests/examples still need manual review.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q48
Use72
Int76
Ver22
Verilogunknown until checkedUART
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.
OpenCores WDSP
DSP/FIR/IIR/FFT
The source appears stale or legacy.
Example of DSP cores with Wishbone and claimed FPGA evidence.
LicenseLGPLLicense riskLGPL: HDL/docs/tests/examples still need manual review.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q48
Use54
Int52
Ver22
VHDLLGPLunknownWishbone
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: github. This is record provenance, not endorsement or quality proof.
IObundle UART16550
peripheral/UART
The license requires manual review.
Modern adaptation of OpenCores UART16550.
LicenseunknownLicense riskunknown: Commercial use is not confirmed.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use54
Int52
Ver40
unknownUART
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: github. This is record provenance, not endorsement or quality proof.
IObundle Ethernet
network/Ethernet
The license requires manual review.
Ethernet candidate with OpenCores ethmac relation.
LicenseunknownLicense riskunknown: Commercial use is not confirmed.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use54
Int52
Ver40
unknownEthernet
PriorityP2 review: entry kept for review depth, edge cases, or future ingestion.Review statusReview status: Unreviewed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.
opencores des core
crypto/DES
The license requires manual review.
Risk model example for obsolete crypto.
LicenseunknownLicense riskunknown: Commercial use is not confirmed.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q34
Use54
Int46
Ver34
Verilog/VHDL unknown until reviewunknown
PriorityP2 review: entry kept for review depth, edge cases, or future ingestion.Review statusReview status: Unreviewed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.
opencores jpeg encoder
video/image processing
The license requires manual review.
Image processing category seed.
LicenseunknownLicense riskunknown: Commercial use is not confirmed.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q34
Use54
Int46
Ver34
Verilog/VHDL unknown until reviewunknown
PriorityP2 review: entry kept for review depth, edge cases, or future ingestion.Review statusReview status: Unreviewed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.
opencores sha256 core
crypto/SHA
The license requires manual review.
Historical hash core.
LicenseunknownLicense riskunknown: Commercial use is not confirmed.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q34
Use54
Int46
Ver34
Verilog/VHDL unknown until reviewunknown
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.
OpenCores Ethernet MAC
network/Ethernet
The license requires manual review.
The source appears stale or legacy.
Important comparison point for LiteEth and IObundle Ethernet.
LicenseunknownLicense riskunknown: Commercial use is not confirmed.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use72
Int52
Ver22
VerilogunknownEthernet
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.
OpenCores I2C controller
peripheral/I2C
The license requires manual review.
The source appears stale or legacy.
Common small peripheral for beginner/professional comparison.
LicenseunknownLicense riskunknown: Commercial use is not confirmed.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use72
Int52
Ver22
VerilogunknownI2C
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.
OpenCores SPI master/slave
peripheral/SPI
The license requires manual review.
The source appears stale or legacy.
Common reusable peripheral baseline.
LicenseunknownLicense riskunknown: Commercial use is not confirmed.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use72
Int52
Ver22
VerilogunknownSPI/QSPI
PriorityP2 review: entry kept for review depth, edge cases, or future ingestion.Review statusReview status: Unreviewed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.
opencores gpio
system/GPIO
The license requires manual review.
Manual review is required.
GPIO category seed.
LicenseunknownLicense riskunknown: Commercial use is not confirmed.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q34
Use54
Int46
Ver34
Verilog/VHDL unknown until reviewunknownGPIO
PriorityP2 review: entry kept for review depth, edge cases, or future ingestion.Review statusReview status: Unreviewed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.
opencores pwm
peripheral/PWM
The license requires manual review.
Manual review is required.
PWM category seed.
LicenseunknownLicense riskunknown: Commercial use is not confirmed.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q34
Use54
Int46
Ver34
Verilog/VHDL unknown until reviewunknownPWM
PriorityP2 review: entry kept for review depth, edge cases, or future ingestion.Review statusReview status: Unreviewed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.
opencores cordic
DSP/CORDIC
The license requires manual review.
Manual review is required.
CORDIC category seed.
LicenseunknownLicense riskunknown: Commercial use is not confirmed.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q34
Use54
Int46
Ver34
Verilog/VHDL unknown until reviewunknown
PriorityP2 review: entry kept for review depth, edge cases, or future ingestion.Review statusReview status: Unreviewed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.
opencores fft
DSP/FFT
The license requires manual review.
Manual review is required.
FFT category seed.
LicenseunknownLicense riskunknown: Commercial use is not confirmed.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q34
Use54
Int46
Ver34
Verilog/VHDL unknown until reviewunknown
PriorityP2 review: entry kept for review depth, edge cases, or future ingestion.Review statusReview status: Unreviewed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.
opencores simple spi
peripheral/SPI
The license requires manual review.
Manual review is required.
Small SPI alternative.
LicenseunknownLicense riskunknown: Commercial use is not confirmed.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q34
Use54
Int46
Ver34
Verilog/VHDL unknown until reviewunknownSPI/QSPI
PriorityP2 review: entry kept for review depth, edge cases, or future ingestion.Review statusReview status: Unreviewed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.
opencores aes core
crypto/AES
The license requires manual review.
The source appears stale or legacy.
Historical AES core to compare with OpenTitan AES.
LicenseunknownLicense riskunknown: Commercial use is not confirmed.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q28
Use54
Int46
Ver22
Verilog/VHDL unknown until reviewunknown
PriorityP2 review: entry kept for review depth, edge cases, or future ingestion.Review statusReview status: Unreviewed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.
opencores can core
peripheral/CAN
The license requires manual review.
The source appears stale or legacy.
CAN/LIN category seed.
LicenseunknownLicense riskunknown: Commercial use is not confirmed.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q28
Use54
Int46
Ver22
Verilog/VHDL unknown until reviewunknown
PriorityP2 review: entry kept for review depth, edge cases, or future ingestion.Review statusReview status: Unreviewed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.
opencores ddr controller
memory/DDR
The license requires manual review.
The source appears stale or legacy.
DDR risk-model example.
LicenseunknownLicense riskunknown: Commercial use is not confirmed.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q28
Use54
Int46
Ver22
Verilog/VHDL unknown until reviewunknownMemory
PriorityP2 review: entry kept for review depth, edge cases, or future ingestion.Review statusReview status: Unreviewed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.
opencores sdram controller
memory/SDRAM
The license requires manual review.
The source appears stale or legacy.
Memory controller comparison.
LicenseunknownLicense riskunknown: Commercial use is not confirmed.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q28
Use54
Int46
Ver22
Verilog/VHDL unknown until reviewunknownMemory
PriorityP2 review: entry kept for review depth, edge cases, or future ingestion.Review statusReview status: Unreviewed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.
opencores usbhostslave
peripheral/USB
The license requires manual review.
The source appears stale or legacy.
USB category seed.
LicenseunknownLicense riskunknown: Commercial use is not confirmed.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q28
Use54
Int46
Ver22
Verilog/VHDL unknown until reviewunknown
PriorityP2 review: entry kept for review depth, edge cases, or future ingestion.Review statusReview status: Unreviewed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.
opencores vga lcd
video/VGA/LCD
The license requires manual review.
The source appears stale or legacy.
Video category seed.
LicenseunknownLicense riskunknown: Commercial use is not confirmed.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q28
Use54
Int46
Ver22
Verilog/VHDL unknown until reviewunknownVGA/HDMI
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.
OpenCores projects directory
directory
The license requires manual review.
The source appears stale or legacy.
Historical baseline and category source.
LicenseunknownLicense riskunknown: Commercial use is not confirmed.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use72
Int52
Ver22
Verilog/VHDL unknown until reviewunknown
PriorityP2 review: entry kept for review depth, edge cases, or future ingestion.Review statusReview status: Unreviewed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.
opencores minsoc
SoC/OpenRISC
The license requires manual review.
The source appears stale or legacy.
Historical SoC integration reference.
LicenseunknownLicense riskunknown: Commercial use is not confirmed.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q28
Use54
Int46
Ver22
Verilog/VHDL unknown until reviewunknown