P0confidence 2/5
OpenTitan IP blocks
High-quality IP block library with docs and verification culture.
Manual review is required.
Cores catalog
FPGA/ASIC/HDL/IP cores
An evidence-first catalog for fast engineering triage: reusable value, license risk, verification depth, and board fit before you open the upstream repo.
How to read cardsA card does not replace upstream docs or license review. Check warnings and commercial-use clarity first, then tests, board evidence, and toolchain fit.Why no featured vendor laneRanking is driven by evidence, review status, and reusable signals. Namespace or vendor identity does not create a privileged lane.
Cores124
P0 launch52
Needs review122
Open flow4
Board linked2
High-risk records in the current index
Submit evidenceP0confidence 2/5
Ibex
Small open RISC-V CPU used by OpenTitan.
Manual review is required.
P0confidence 2/5
LiteX
Central open SoC builder and integration framework.
Manual review is required.
P0confidence 2/5
OpenCores Wishbone
Bus protocol reference for OpenCores-era reusable IP.
Manual review is required.
P0confidence 2/5
OpenCores WBScope
Useful Wishbone-accessible debug core by ZipCPU author.
Manual review is required.
Catalog
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: github. This is record provenance, not endorsement or quality proof.
Open Logic AXI/base/intf
library/interfaces/math
The license requires manual review.
FuseSoC-listed open logic package family.
LicenseunknownLicense riskunknown: Commercial use is not confirmed.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use54
Int76
Ver40
unknownAXI
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: github. This is record provenance, not endorsement or quality proof.
ZipCPU wb2axip
bus bridge/formal
The license requires manual review.
Wishbone/AXI bridge and formal property library.
LicenseunknownLicense riskunknown: Commercial use is not confirmed.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use72
Int52
Ver40
VerilogunknownWishboneAXI
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: github. This is record provenance, not endorsement or quality proof.
pulp-platform axi
bus/AXI
The license requires manual review.
AXI components and infrastructure.
LicenseunknownLicense riskunknown: Commercial use is not confirmed.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use72
Int52
Ver40
SystemVerilogunknownAXI
PriorityP1 expansion: useful candidate after the baseline P0 set.Review statusReview status: Unreviewed. Manual review is still required beyond seed/index metadata.Source typeSource type: github. This is record provenance, not endorsement or quality proof.
verilog-axi
bus/AXI
The license requires manual review.
AXI component library and comparison source.
LicenseunknownLicense riskunknown: Commercial use is not confirmed.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use72
Int49
Ver37
unknownAXI
PriorityP1 expansion: useful candidate after the baseline P0 set.Review statusReview status: Unreviewed. Manual review is still required beyond seed/index metadata.Source typeSource type: github. This is record provenance, not endorsement or quality proof.
taxi
bus/AXI/stream
The license requires manual review.
Successor ecosystem for AXI/stream components.
LicenseunknownLicense riskunknown: Commercial use is not confirmed.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use54
Int49
Ver37
unknownFIFO/streamAXI
PriorityP2 review: entry kept for review depth, edge cases, or future ingestion.Review statusReview status: Unreviewed. Manual review is still required beyond seed/index metadata.Source typeSource type: vendor examples. This is record provenance, not endorsement or quality proof.
vendor Xilinx AXI examples
vendor/examples
The license requires manual review.
There is a vendor tooling or license constraint.
Useful reference only if license permits.
LicenseunknownLicense riskunknown: Commercial use is not confirmed.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q34
Use54
Int46
Ver34
unknownAXI
PriorityP1 expansion: useful candidate after the baseline P0 set.Review statusReview status: Unreviewed. Manual review is still required beyond seed/index metadata.Source typeSource type: github. This is record provenance, not endorsement or quality proof.
verilog-axis
bus/AXI-Stream
The license requires manual review.
AXI-Stream component library.
LicenseunknownLicense riskunknown: Commercial use is not confirmed.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use72
Int49
Ver37
unknownFIFO/streamAXI