Starter Tang board on Gowin GW1NR-9: 8640 LUT4, HDMI, TF slot, USB-JTAG, and USB-UART.
SipeedGowinEducation
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GW2AR-18 board: 20736 LUT4, SDR SDRAM, HDMI, TF slot, and BL616 debugger.
SipeedGowinEducation
23x18 mm core board on GW5A-LV25MG121 plus dock with USB-C debugger, PMOD, and SDRAM connector.
SipeedGowinFPGA + SoC
Yosys is a baseline open-source framework for Verilog RTL synthesis and formal-related flows.
Open-sourceYosysVerilog / SystemVerilog
nextpnr supports multiple FPGA families, including Gowin through Project Apicula.
Open-sourceYosysGowin
Verilator compiles Verilog/SystemVerilog into C++/SystemC and is used in regression flows.
Open-sourceVerilatorVerilog / SystemVerilog
LiteX builds FPGA cores and SoCs and supports mixed-language integration around a Python flow.
Open-sourceLiteXRISC-V
AMD’s new engineering article covers system-level verification for Versal designs that combine PL, AI Engines, NoC, and software.
AMD / XilinxEducationVerilog / SystemVerilog
The Vitis 2025.2 tutorial shows a system FIR flow for Versal with AI Engines, HLS, and programmable logic.
AMD / XilinxEducationFPGA + SoC
AN4792 describes a high-speed data transfer demo on PolarFire FPGA using LiteFast IP, 8b10b mode, and a loopback setup.
MicrochipEducationFPGA + SoC