News
YADRO announces SoC Design Challenge 2027
October 8, 2026· YADRO FPGA event coverage· Note
YADRO’s education catalogue lists a three-day hackathon in Moscow in 2027. Exact dates and participation requirements remain unannounced.
Verilog / SystemVerilogFPGA + SoCEducationRISC-V
Announcement
YADRO’s catalogue lists SoC Design Challenge 2027: a three-day RISC-V processor-design hackathon in Moscow for students and experienced engineers. Registration is listed for 2027.
Details still pending
Exact dates, venue and 2027 competition tracks have not been published. The linked challenge page still describes 24–26 April 2026. Checked on 8 October 2026; the previous edition’s dates do not apply to the new announcement.