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Projects

Open-source FPGA projects

RTL, tooling, boards, labs.

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All projectsOpen-sourceYosysRISC-VFPGA + SoC

2 results

Topic: YosysClear filters
Maintainedgithub.comApril 26, 2026ISC
nextpnr

Portable FPGA place-and-route tool with support for several FPGA families.

C++PnRGowinECP5Open-sourceYosys
Repository
Maintainedgithub.comApril 26, 2026ISC
Yosys

Open SYnthesis Suite for Verilog RTL synthesis and formal-related flows.

VerilogRTLILSynthesisFormalOpen-sourceYosys+1
Repository

Publication criteria

This catalog has few published projects. Only real records with a repository or verifiable source are shown; unverified projects are not created.

Repository URLLicense and statusMaintainer or source evidenceFPGA/RTL/tooling scope
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Results indexTopics: 4Stack: 8
Topics
Open-source2Yosys2Gowin1Verilog / SystemVerilog1
Stack
C++1ECP51Formal1Gowin1PnR1RTLIL1Synthesis1Verilog1