P0 Auto indexed github
security/root-of-trust/IP blocks
High-quality IP block library with docs and verification culture.
License Apache-2.0 Lower commercial risk
1 Evidence Public evidence links attached to this record. 0 Boards Board-linked compatibility records, not portability guarantees. 2/5 Confidence How strongly the current record is backed by reviewed evidence. SystemVerilog Apache-2.0 unknown
Warning Manual review is required.
P0 Auto indexed github
Small open RISC-V CPU used by OpenTitan.
License Apache-2.0 Lower commercial risk
1 Evidence Public evidence links attached to this record. 0 Boards Board-linked compatibility records, not portability guarantees. 2/5 Confidence How strongly the current record is backed by reviewed evidence. SystemVerilog Apache-2.0 unknown
Warning Manual review is required.
P0 Auto indexed github
Central open SoC builder and integration framework.
License BSD-2-Clause-like until checked Lower commercial risk
1 Evidence Public evidence links attached to this record. 0 Boards Board-linked compatibility records, not portability guarantees. 2/5 Confidence How strongly the current record is backed by reviewed evidence. Migen/Python/Verilog BSD-2-Clause-like until checked Memory
Warning Manual review is required.
P0 Auto indexed opencores
Bus protocol reference for OpenCores-era reusable IP.
License public-domain-like per OpenCores WISHBONE page License needs review
1 Evidence Public evidence links attached to this record. 0 Boards Board-linked compatibility records, not portability guarantees. 2/5 Confidence How strongly the current record is backed by reviewed evidence. Specification public-domain-like per OpenCores WISHBONE page unknown Wishbone
Warning Manual review is required.
P0 Auto indexed opencores
verification/logic analyzer
Useful Wishbone-accessible debug core by ZipCPU author.
License GPL License needs review
1 Evidence Public evidence links attached to this record. 0 Boards Board-linked compatibility records, not portability guarantees. 2/5 Confidence How strongly the current record is backed by reviewed evidence. Verilog GPL JTAG/debug Wishbone
Warning Manual review is required.
P0 Auto indexed opencores
Canonical UART reference and common FuseSoC adaptations.
License unknown until checked License needs review
1 Evidence Public evidence links attached to this record. 0 Boards Board-linked compatibility records, not portability guarantees. 2/5 Confidence How strongly the current record is backed by reviewed evidence. Verilog unknown until checked UART
Warning The license requires manual review.
High The source appears stale or legacy.
P0 Auto indexed github
Industrial-grade open RISC-V core family source.
License Solderpad License needs review
1 Evidence Public evidence links attached to this record. 0 Boards Board-linked compatibility records, not portability guarantees. 2/5 Confidence How strongly the current record is backed by reviewed evidence. SystemVerilog Solderpad unknown
Warning Manual review is required.
P2 Unreviewed github_org
namespace/AccelFury cores
Namespace index for public AccelFury repositories; useful as one source among many, not as a catalog priority lane.
License per-repository License needs review
1 Evidence Public evidence links attached to this record. 0 Boards Board-linked compatibility records, not portability guarantees. 1/5 Confidence How strongly the current record is backed by reviewed evidence. mixed per-repository unknown
Warning Manual review is required.
P0 Auto indexed github
Large curated arcade FPGA core ecosystem.
License GPL-3.0 License needs review
1 Evidence Public evidence links attached to this record. 0 Boards Board-linked compatibility records, not portability guarantees. 2/5 Confidence How strongly the current record is backed by reviewed evidence. Verilog GPL-3.0 unknown
Critical There is legal risk around ROM/retro assets.
P1 Manually reviewed github
audio / sensor interface / PDM RX
Raw PDM RX core на Verilog-2001 для MEMS microphones: генерирует PDM clock, сэмплирует 1-битный поток и выдаёт valid/ready stream. Не выполняет PDM-to-PCM decimation.
License AccelFury Source Available Source-available limitation
1 Evidence Public evidence links attached to this record. 2 Boards Board-linked compatibility records, not portability guarantees. 1/5 Confidence How strongly the current record is backed by reviewed evidence. Verilog-2001 AccelFury Source Available PDM
Critical Source is available, but commercial use may require a separate license.
Info The core does not include a decimator/CIC/FIR pipeline.
