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Production candidates

Не “production-ready”: кандидаты, где ожидаются сильные evidence и review.

PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: github. This is record provenance, not endorsement or quality proof.

OpenTitan IP blocks

security/root-of-trust/IP blocks

Warning

Manual review is required.

High-quality IP block library with docs and verification culture.

LicenseApache-2.0License riskApache-2.0: Current metadata does not show an explicit license blocker.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q54
Use72
Int52
Ver40
SystemVerilogApache-2.0unknown
Open recordCompareSource
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: github. This is record provenance, not endorsement or quality proof.

Ibex

processor/RISC-V

Warning

Manual review is required.

Small open RISC-V CPU used by OpenTitan.

LicenseApache-2.0License riskApache-2.0: Current metadata does not show an explicit license blocker.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q54
Use72
Int52
Ver40
SystemVerilogApache-2.0unknown
Open recordCompareSource
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: github. This is record provenance, not endorsement or quality proof.

LiteX

SoC builder/generator

Warning

Manual review is required.

Central open SoC builder and integration framework.

LicenseBSD-2-Clause-like until checkedLicense riskBSD-2-Clause-like until checked: Current metadata does not show an explicit license blocker.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q54
Use72
Int52
Ver40
Migen/Python/VerilogBSD-2-Clause-like until checkedMemory
Open recordCompareSource
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.

OpenCores Wishbone

bus/Wishbone

Warning

Manual review is required.

Bus protocol reference for OpenCores-era reusable IP.

Licensepublic-domain-like per OpenCores WISHBONE pageLicense riskpublic-domain-like per OpenCores WISHBONE page: HDL/docs/tests/examples still need manual review.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q54
Use54
Int52
Ver18
Specificationpublic-domain-like per OpenCores WISHBONE pageunknownWishbone
Open recordCompareSource
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.

OpenCores WBScope

verification/logic analyzer

Warning

Manual review is required.

Useful Wishbone-accessible debug core by ZipCPU author.

LicenseGPLLicense riskGPL: HDL/docs/tests/examples still need manual review.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q54
Use72
Int52
Ver40
VerilogGPLJTAG/debugWishbone
Open recordCompareSource
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.

OpenCores UART16550

peripheral/UART

Warning

The license requires manual review.

High

The source appears stale or legacy.

Canonical UART reference and common FuseSoC adaptations.

Licenseunknown until checkedLicense riskunknown until checked: HDL/docs/tests/examples still need manual review.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q48
Use72
Int76
Ver22
Verilogunknown until checkedUART
Open recordCompareSource
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: github. This is record provenance, not endorsement or quality proof.

OpenHW CORE-V cores

processor/RISC-V

Warning

Manual review is required.

Industrial-grade open RISC-V core family source.

LicenseSolderpadLicense riskSolderpad: HDL/docs/tests/examples still need manual review.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q54
Use72
Int52
Ver40
SystemVerilogSolderpadunknown
Open recordCompareSource
PriorityP2 review: entry kept for review depth, edge cases, or future ingestion.Review statusReview status: Unreviewed. Manual review is still required beyond seed/index metadata.Source typeSource type: github org. This is record provenance, not endorsement or quality proof.

AccelFury organization page

namespace/AccelFury cores

Warning

Manual review is required.

Namespace index for public AccelFury repositories; useful as one source among many, not as a catalog priority lane.

Licenseper-repositoryLicense riskper-repository: HDL/docs/tests/examples still need manual review.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q42
Use72
Int46
Ver34
mixedper-repositoryunknown
Open recordCompareSource
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: github. This is record provenance, not endorsement or quality proof.

jotego jtcores

retro/arcade

Critical

There is legal risk around ROM/retro assets.

Large curated arcade FPGA core ecosystem.

LicenseGPL-3.0License riskGPL-3.0: HDL/docs/tests/examples still need manual review.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q54
Use72
Int52
Ver40
VerilogGPL-3.0unknown
Open recordCompareSource
PriorityP1 expansion: useful candidate after the baseline P0 set.Review statusReview status: Manually reviewed. A manual pass exists, but evidence still needs link-level checking.Source typeSource type: github. This is record provenance, not endorsement or quality proof.

AccelFury af-pdm-rx

audio / sensor interface / PDM RX

Critical

Source is available, but commercial use may require a separate license.

Info

The core does not include a decimator/CIC/FIR pipeline.

Raw PDM RX core на Verilog-2001 для MEMS microphones: генерирует PDM clock, сэмплирует 1-битный поток и выдаёт valid/ready stream. Не выполняет PDM-to-PCM decimation.

LicenseAccelFury Source AvailableLicense riskAccelFury Source Available: A separate commercial license may be required.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q48
Use72
Int49
Ver37
Verilog-2001AccelFury Source AvailablePDM
Open recordCompareSource