Cores
Open HDL cores for FPGA. License, tests and activity checked on GitHub.
| Core | Maturity | License | Language | Activity |
|---|---|---|---|---|
| OpenTitan prim library Buses and infrastructure | M4 · Production-ready | Apache-2.0 | — | updated today |
| wb_intercon Buses and infrastructure | M2 · Simulation-tested | ISC | — | updated 7 months ago |
| verilog-axi Buses and infrastructure | M2 · Simulation-tested | MIT | — | updated 2 years ago |
| verilog-axis Buses and infrastructure | M2 · Simulation-tested | MIT | — | updated 2 years ago |
| stream_utils Buses and infrastructure | M2 · Simulation-tested | ISC | — | updated 12 months ago |
| taxi Buses and infrastructure | M2 · Simulation-tested | CERN-OHL-S-2.0 | — | updated 34 days ago |
| colibri Buses and infrastructure | M1 · Prototype | CERN-OHL-W-2.0 | VHDL-2008 | — |
| pulp-platform common_cells Buses and infrastructure | M4 · Production-ready | No license found | SystemVerilog | updated 14 days ago |
| ZipCPU wb2axip Buses and infrastructure | M2 · Simulation-tested | No license found | Verilog | updated 21 days ago |
| Open Logic AXI/base/intf Buses and infrastructure | M4 · Production-ready | No license found | — | updated 4 days ago |
| pulp-platform axi Buses and infrastructure | M4 · Production-ready | No license found | SystemVerilog | updated 8 days ago |
| BaseJump STL Buses and infrastructure | M2 · Simulation-tested | No license found | — | updated 4 days ago |
| cdc_utils Buses and infrastructure | M1 · Prototype | No license found | — | — |
| OpenTitan GPIO IP Buses and infrastructure | M1 · Prototype | No license found | — | — |
| opencores gpio Buses and infrastructure | M1 · Prototype | No license found | Verilog/VHDL unknown until review | — |