Cores
Open HDL cores for FPGA. License, tests and activity checked on GitHub.
| Core | Maturity | License | Language | Activity |
|---|---|---|---|---|
| Project F display controller Audio and video | M2 · Simulation-tested | MIT | — | updated 8 months ago |
| jotego JT12 Audio and video | M2 · Simulation-tested | GPL-3.0 | Verilog | updated 31 days ago |
| jt51 Audio and video | M2 · Simulation-tested | GPL-3.0 | — | updated 2 months ago |
| jtopl Audio and video | M2 · Simulation-tested | GPL-3.0 | — | updated 2 months ago |
| AccelFury af-pdm-rx Audio and video | M1 · Prototype | AccelFury Source Available | Verilog-2001 | — |
| hdl-util HDMI Audio and video | M4 · Production-ready | No license found | Verilog/VHDL | updated 3 months ago |
| hdl-util VGA Audio and video | M1 · Prototype | No license found | — | — |
| opencores jpeg encoder Audio and video | M1 · Prototype | No license found | Verilog/VHDL unknown until review | — |
| opencores vga lcd Audio and video | M1 · Prototype | No license found | Verilog/VHDL unknown until review | — |