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Cores catalog

FPGA/ASIC/HDL/IP cores

An evidence-first catalog for fast engineering triage: reusable value, license risk, verification depth, and board fit before you open the upstream repo.

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How to read cardsA card does not replace upstream docs or license review. Check warnings and commercial-use clarity first, then tests, board evidence, and toolchain fit.Why no featured vendor laneRanking is driven by evidence, review status, and reusable signals. Namespace or vendor identity does not create a privileged lane.
Cores124
P0 launch52
Needs review122
Open flow4
Board linked2

High-risk records in the current index

Submit evidence
P0confidence 2/5

OpenTitan IP blocks

High-quality IP block library with docs and verification culture.

Warning

Manual review is required.

P0confidence 2/5

Ibex

Small open RISC-V CPU used by OpenTitan.

Warning

Manual review is required.

P0confidence 2/5

LiteX

Central open SoC builder and integration framework.

Warning

Manual review is required.

P0confidence 2/5

OpenCores Wishbone

Bus protocol reference for OpenCores-era reusable IP.

Warning

Manual review is required.

P0confidence 2/5

OpenCores WBScope

Useful Wishbone-accessible debug core by ZipCPU author.

Warning

Manual review is required.

Catalog

What is surfacedThe index already surfaces warnings, evidence counts, board links, and review depth. That is enough for triage, but not for a final verdict.8 records
CoreLicense / reviewSignalsInterfaces / flowWarnings
LiteXSoC builder/generator
P0Auto indexedgithub

Central open SoC builder and integration framework.

BSD-2-Clause-like until checkedLower commercial riskM6
Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale.
Migen/Python/VerilogMemoryunknownLiteX, Verilator
Manual review is required.
LiteDRAMmemory/DRAM
P0Auto indexedgithub

Open DRAM controller ecosystem used with LiteX.

unknownNo clear licenseM1-M3 candidate
Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale.
Migen/Python/VerilogMemoryunknownLiteX, Verilator
The license requires manual review.
fifomemory/FIFO
P0Auto indexedgithub

Generic FIFO baseline.

unknownNo clear licenseM1-M3 candidate
Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale.
unknownFIFO/stream, Memoryunknownunknown
The license requires manual review.
IObundle cachememory/cache
P0Auto indexedgithub

Open cache candidate.

unknownNo clear licenseM1-M3 candidate
Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale.
unknownMemoryunknownunknown
The license requires manual review.
wb_rammemory/Wishbone RAM
P0Auto indexedgithub

Minimal SoC building block.

unknownNo clear licenseM1-M3 candidate
Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale.
unknownMemoryWishboneunknown
The license requires manual review.
LiteHyperBusmemory/HyperBus
P1Unreviewedgithub

HyperRAM/HyperFlash ecosystem core.

unknownNo clear licenseunknown
Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale.
unknownMemoryunknownunknown
The license requires manual review.
opencores ddr controllermemory/DDR
P2Unreviewedopencores

DDR risk-model example.

unknownNo clear licenseunknown
Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale.
Verilog/VHDL unknown until reviewMemoryunknownunknown
The license requires manual review.The source appears stale or legacy.
opencores sdram controllermemory/SDRAM
P2Unreviewedopencores

Memory controller comparison.

unknownNo clear licenseunknown
Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale.
Verilog/VHDL unknown until reviewMemoryunknownunknown
The license requires manual review.The source appears stale or legacy.