Sign in
Cores catalog

FPGA/ASIC/HDL/IP cores

An evidence-first catalog for fast engineering triage: reusable value, license risk, verification depth, and board fit before you open the upstream repo.

Submit a core
How to read cardsA card does not replace upstream docs or license review. Check warnings and commercial-use clarity first, then tests, board evidence, and toolchain fit.Why no featured vendor laneRanking is driven by evidence, review status, and reusable signals. Namespace or vendor identity does not create a privileged lane.
Cores124
P0 launch52
Needs review122
Open flow4
Board linked2

High-risk records in the current index

Submit evidence
P0confidence 2/5

OpenTitan IP blocks

High-quality IP block library with docs and verification culture.

Warning

Manual review is required.

P0confidence 2/5

Ibex

Small open RISC-V CPU used by OpenTitan.

Warning

Manual review is required.

P0confidence 2/5

LiteX

Central open SoC builder and integration framework.

Warning

Manual review is required.

P0confidence 2/5

OpenCores Wishbone

Bus protocol reference for OpenCores-era reusable IP.

Warning

Manual review is required.

P0confidence 2/5

OpenCores WBScope

Useful Wishbone-accessible debug core by ZipCPU author.

Warning

Manual review is required.

Catalog

What is surfacedThe index already surfaces warnings, evidence counts, board links, and review depth. That is enough for triage, but not for a final verdict.7 records
CoreLicense / reviewSignalsInterfaces / flowWarnings
Open Logic AXI/base/intflibrary/interfaces/math
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: github. This is record provenance, not endorsement or quality proof.

FuseSoC-listed open logic package family.

unknownLicense riskunknown: Commercial use is not confirmed.M1-M3 candidateMaturity levelMaturity M1-M3 candidate: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale.
Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale.
unknownunknownAXIFuseSoC
The license requires manual review.
ZipCPU wb2axipbus bridge/formal
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: github. This is record provenance, not endorsement or quality proof.

Wishbone/AXI bridge and formal property library.

unknownLicense riskunknown: Commercial use is not confirmed.M1-M3 candidateMaturity levelMaturity M1-M3 candidate: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale.
Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale.
VerilogunknownWishbone, AXIVerilator
The license requires manual review.
pulp-platform axibus/AXI
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: github. This is record provenance, not endorsement or quality proof.

AXI components and infrastructure.

unknownLicense riskunknown: Commercial use is not confirmed.M1-M3 candidateMaturity levelMaturity M1-M3 candidate: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale.
Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale.
SystemVerilogunknownAXIVerilator
The license requires manual review.
verilog-axibus/AXI
PriorityP1 expansion: useful candidate after the baseline P0 set.Review statusReview status: Unreviewed. Manual review is still required beyond seed/index metadata.Source typeSource type: github. This is record provenance, not endorsement or quality proof.

AXI component library and comparison source.

unknownLicense riskunknown: Commercial use is not confirmed.unknownMaturity levelMaturity unknown: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale.
Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale.
unknownunknownAXIVerilator
The license requires manual review.
taxibus/AXI/stream
PriorityP1 expansion: useful candidate after the baseline P0 set.Review statusReview status: Unreviewed. Manual review is still required beyond seed/index metadata.Source typeSource type: github. This is record provenance, not endorsement or quality proof.

Successor ecosystem for AXI/stream components.

unknownLicense riskunknown: Commercial use is not confirmed.unknownMaturity levelMaturity unknown: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale.
Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale.
unknownFIFO/streamAXIunknown
The license requires manual review.
vendor Xilinx AXI examplesvendor/examples
PriorityP2 review: entry kept for review depth, edge cases, or future ingestion.Review statusReview status: Unreviewed. Manual review is still required beyond seed/index metadata.Source typeSource type: vendor examples. This is record provenance, not endorsement or quality proof.

Useful reference only if license permits.

unknownLicense riskunknown: Commercial use is not confirmed.unknownMaturity levelMaturity unknown: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale.
Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale.
unknownunknownAXIVivado
The license requires manual review.There is a vendor tooling or license constraint.
verilog-axisbus/AXI-Stream
PriorityP1 expansion: useful candidate after the baseline P0 set.Review statusReview status: Unreviewed. Manual review is still required beyond seed/index metadata.Source typeSource type: github. This is record provenance, not endorsement or quality proof.

AXI-Stream component library.

unknownLicense riskunknown: Commercial use is not confirmed.unknownMaturity levelMaturity unknown: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale.
Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale.
unknownFIFO/streamAXIVerilator
The license requires manual review.