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Cores catalog

FPGA/ASIC/HDL/IP cores

An evidence-first catalog for fast engineering triage: reusable value, license risk, verification depth, and board fit before you open the upstream repo.

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How to read cardsA card does not replace upstream docs or license review. Check warnings and commercial-use clarity first, then tests, board evidence, and toolchain fit.Why no featured vendor laneRanking is driven by evidence, review status, and reusable signals. Namespace or vendor identity does not create a privileged lane.
Cores124
P0 launch52
Needs review122
Open flow4
Board linked2

High-risk records in the current index

Submit evidence
P0confidence 2/5

OpenTitan IP blocks

High-quality IP block library with docs and verification culture.

Warning

Manual review is required.

P0confidence 2/5

Ibex

Small open RISC-V CPU used by OpenTitan.

Warning

Manual review is required.

P0confidence 2/5

LiteX

Central open SoC builder and integration framework.

Warning

Manual review is required.

P0confidence 2/5

OpenCores Wishbone

Bus protocol reference for OpenCores-era reusable IP.

Warning

Manual review is required.

P0confidence 2/5

OpenCores WBScope

Useful Wishbone-accessible debug core by ZipCPU author.

Warning

Manual review is required.

Catalog

What is surfacedThe index already surfaces warnings, evidence counts, board links, and review depth. That is enough for triage, but not for a final verdict.1 records
P2Unreviewedcommunity/projects

Hackaday FPGA projects

projects/reference designs

Discovery source for reference designs and board demos.

LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q34
Use54
Int46
Ver34
unknown
Warning

The license requires manual review.

Open recordCompareSource