FPGA community hub

The April 30, 2026 release promises streaming AI-model mapping onto Agilex FPGAs for deterministic edge inference.

The Lattice solution with NVIDIA Holoscan Sensor Bridge combines a CertusPro-NX sensor-to-Ethernet board with an edge AI data path.

Lattice announced an Embedded Vision Summit 2026 demo program and expert session around edge AI, computer vision, sensor bridging, and robotics.

FPGA.camp opened its first version as a compact engineering hub: news, journal, projects, classifieds, meetups, boards, KB, and Chat.

Yosys is a baseline open-source framework for Verilog RTL synthesis and formal-related flows.

nextpnr supports multiple FPGA families, including Gowin through Project Apicula.

Verilator compiles Verilog/SystemVerilog into C++/SystemC and is used in regression flows.

LiteX builds FPGA cores and SoCs and supports mixed-language integration around a Python flow.

The /chat section accepts FPGA questions and sends them through a server-side OpenRouter endpoint.

PIC16F13276 and PIC18-Q35 combine an MCU with CPLD-like programmable logic for timing-critical embedded work.

AMD’s new engineering article covers system-level verification for Versal designs that combine PL, AI Engines, NoC, and software.

Agilex, MAX 10, and Cyclone V get planned long-term support that matters for industrial, aerospace, medical, and transportation systems.