P0confidence 2/5
OpenTitan IP blocks
High-quality IP block library with docs and verification culture.
Manual review is required.
Cores catalog
FPGA/ASIC/HDL/IP cores
An evidence-first catalog for fast engineering triage: reusable value, license risk, verification depth, and board fit before you open the upstream repo.
How to read cardsA card does not replace upstream docs or license review. Check warnings and commercial-use clarity first, then tests, board evidence, and toolchain fit.Why no featured vendor laneRanking is driven by evidence, review status, and reusable signals. Namespace or vendor identity does not create a privileged lane.
Cores124
P0 launch52
Needs review122
Open flow4
Board linked2
High-risk records in the current index
Submit evidenceP0confidence 2/5
Ibex
Small open RISC-V CPU used by OpenTitan.
Manual review is required.
P0confidence 2/5
LiteX
Central open SoC builder and integration framework.
Manual review is required.
P0confidence 2/5
OpenCores Wishbone
Bus protocol reference for OpenCores-era reusable IP.
Manual review is required.
P0confidence 2/5
OpenCores WBScope
Useful Wishbone-accessible debug core by ZipCPU author.
Manual review is required.
Catalog
P0Auto indexedgithub
LiteX
SoC builder/generator
Central open SoC builder and integration framework.
LicenseBSD-2-Clause-like until checkedLower commercial risk
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q54
Use72
Int52
Ver40
Migen/Python/VerilogBSD-2-Clause-like until checkedMemory
Manual review is required.
P0Auto indexedgithub
LiteDRAM
memory/DRAM
Open DRAM controller ecosystem used with LiteX.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use72
Int76
Ver40
Migen/Python/VerilogunknownMemory
The license requires manual review.
P0Auto indexedgithub
fifo
memory/FIFO
Generic FIFO baseline.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use54
Int52
Ver40
unknownFIFO/streamMemory
The license requires manual review.
P0Auto indexedgithub
IObundle cache
memory/cache
Open cache candidate.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use54
Int52
Ver40
unknownMemory
The license requires manual review.
P0Auto indexedgithub
wb_ram
memory/Wishbone RAM
Minimal SoC building block.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use54
Int52
Ver40
unknownMemoryWishbone
The license requires manual review.
P1Unreviewedgithub
LiteHyperBus
memory/HyperBus
HyperRAM/HyperFlash ecosystem core.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use54
Int49
Ver37
unknownMemory
The license requires manual review.
P2Unreviewedopencores
opencores ddr controller
memory/DDR
DDR risk-model example.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q28
Use54
Int46
Ver22
Verilog/VHDL unknown until reviewunknownMemory
The license requires manual review.
The source appears stale or legacy.
P2Unreviewedopencores
opencores sdram controller
memory/SDRAM
Memory controller comparison.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q28
Use54
Int46
Ver22
Verilog/VHDL unknown until reviewunknownMemory
The license requires manual review.
The source appears stale or legacy.