Cores
Open HDL cores for FPGA. License, tests and activity checked on GitHub.
| Core | Maturity | License | Language | Activity |
|---|---|---|---|---|
| ZipCPU wb2axip Buses and infrastructure | M2 · Simulation-tested | No license found | Verilog | updated 21 days ago |
| CORE-V-VERIF Verification and debug | M4 · Production-ready | No license found | SystemVerilog/UVM | updated 18 days ago |
| MiSTer SNES Retro | M2 · Simulation-tested | GPL-3.0 | — | updated 15 days ago |
| Open Logic AXI/base/intf Buses and infrastructure | M4 · Production-ready | No license found | — | updated 4 days ago |
| pulp-platform axi Buses and infrastructure | M4 · Production-ready | No license found | SystemVerilog | updated 8 days ago |
| OpenRISC mor1kx CPUs and compute | M4 · Production-ready | No license found | Verilog | updated 4 months ago |
| ZipCPU CPUs and compute | M2 · Simulation-tested | No license found | Verilog | updated 16 days ago |
| IObundle UART16550 Interfaces and peripherals | M4 · Production-ready | No license found | — | updated 11 days ago |
| OpenCores WBScope Verification and debug | M1 · Prototype | GPL | Verilog | — |
| LiteDRAM Memory and storage | M2 · Simulation-tested | No license found | Migen/Python/Verilog | updated 8 days ago |
| LiteEth Interfaces and peripherals | M2 · Simulation-tested | No license found | Migen/Python/Verilog | updated 4 days ago |
| LiteSATA Memory and storage | M2 · Simulation-tested | No license found | Migen/Python/Verilog | updated 8 days ago |
| LiteScope Verification and debug | M2 · Simulation-tested | No license found | Migen/Python/Verilog | updated 8 days ago |
| LiteSDCard Memory and storage | M2 · Simulation-tested | No license found | Migen/Python/Verilog | updated 8 days ago |
| Wally RISC-V CPUs and compute | M4 · Production-ready | No license found | SystemVerilog | updated 8 days ago |
| wb_bfm Verification and debug | M2 · Simulation-tested | No license found | — | updated 9 years ago |
| fifo Memory and storage | M2 · Simulation-tested | No license found | — | updated 6 years ago |
| Berkeley HardFloat CPUs and compute | M2 · Simulation-tested | No license found | — | updated 44 days ago |
| LiteICLink Interfaces and peripherals | M2 · Simulation-tested | No license found | — | updated 4 days ago |
| LiteJESD204B DSP and radio | M2 · Simulation-tested | No license found | — | updated 8 days ago |
| MiSTer NES Retro | M1 · Prototype | GPL-3.0 | — | updated 16 days ago |
| Rocket Chip CPUs and compute | M1 · Prototype | No license found | — | updated 19 days ago |
| AccelFury af-pdm-rx Audio and video | M1 · Prototype | AccelFury Source Available | Verilog-2001 | — |
| OpenCores WDSP DSP and radio | M1 · Prototype | LGPL | VHDL | — |