Cores

Open HDL cores for FPGA. License, tests and activity checked on GitHub.

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106 results · Page 3 of 5

Cards Table

ZipCPU wb2axip

Checked on GitHub

Wishbone/AXI bridge and formal property library.

Buses and infrastructureVerilogNo license foundM2 · Simulation-testedupdated 21 days ago

CORE-V-VERIF

Checked on GitHub

Verification evidence model for CORE-V cores.

Verification and debugSystemVerilog/UVMNo license foundM4 · Production-readyupdated 18 days ago

MiSTer SNES

Checked on GitHub

Console core example.

RetroGPL-3.0M2 · Simulation-testedupdated 15 days ago

Open Logic AXI/base/intf

Checked on GitHub

FuseSoC-listed open logic package family.

Buses and infrastructureNo license foundM4 · Production-readyupdated 4 days ago

pulp-platform axi

Checked on GitHub

AXI components and infrastructure.

Buses and infrastructureSystemVerilogNo license foundM4 · Production-readyupdated 8 days ago

OpenRISC mor1kx

Checked on GitHub

OpenRISC core relevant to Wishbone history.

CPUs and computeVerilogNo license foundM4 · Production-readyupdated 4 months ago

ZipCPU

Checked on GitHub

CPU, Wishbone and formal-heavy ecosystem.

CPUs and computeVerilogNo license foundM2 · Simulation-testedupdated 16 days ago

IObundle UART16550

Checked on GitHub

Modern adaptation of OpenCores UART16550.

Interfaces and peripheralsNo license foundM4 · Production-readyupdated 11 days ago

OpenCores WBScope

Useful Wishbone-accessible debug core by ZipCPU author.

Verification and debugVerilogGPLM1 · Prototype

LiteDRAM

Checked on GitHub

Open DRAM controller ecosystem used with LiteX.

Memory and storageMigen/Python/VerilogNo license foundM2 · Simulation-testedupdated 8 days ago

LiteEth

Checked on GitHub

Modern Ethernet core comparison point.

Interfaces and peripheralsMigen/Python/VerilogNo license foundM2 · Simulation-testedupdated 4 days ago

LiteSATA

Checked on GitHub

High-value storage/networked design reference.

Memory and storageMigen/Python/VerilogNo license foundM2 · Simulation-testedupdated 8 days ago

LiteScope

Checked on GitHub

Debug infrastructure for composition planner.

Verification and debugMigen/Python/VerilogNo license foundM2 · Simulation-testedupdated 8 days ago

LiteSDCard

Checked on GitHub

Useful storage peripheral for SoC designs.

Memory and storageMigen/Python/VerilogNo license foundM2 · Simulation-testedupdated 8 days ago

Wally RISC-V

Checked on GitHub

Open RISC-V core family for comparison.

CPUs and computeSystemVerilogNo license foundM4 · Production-readyupdated 8 days ago

wb_bfm

Checked on GitHub

Verification helper for Wishbone cores.

Verification and debugNo license foundM2 · Simulation-testedupdated 9 years ago

fifo

Checked on GitHub

Generic FIFO baseline.

Memory and storageNo license foundM2 · Simulation-testedupdated 6 years ago

Berkeley HardFloat

Checked on GitHub

Floating-point arithmetic core family.

CPUs and computeNo license foundM2 · Simulation-testedupdated 44 days ago

LiteICLink

Checked on GitHub

LiteX complex link core.

Interfaces and peripheralsNo license foundM2 · Simulation-testedupdated 4 days ago

LiteJESD204B

Checked on GitHub

JESD204B open core candidate.

DSP and radioNo license foundM2 · Simulation-testedupdated 8 days ago

MiSTer NES

Checked on GitHub

Console core example.

RetroGPL-3.0M1 · Prototypeupdated 16 days ago

Rocket Chip

Checked on GitHub

Important Chisel generator ecosystem.

CPUs and computeNo license foundM1 · Prototypeupdated 19 days ago

AccelFury af-pdm-rx

Verilog-2001 PDM receiver for MEMS microphones. Generates the PDM clock and outputs a one-bit valid/ready stream. Does not convert PDM to PCM.

Audio and videoVerilog-2001Custom licenseM1 · Prototype

OpenCores WDSP

Example of DSP cores with Wishbone and claimed FPGA evidence.

DSP and radioVHDLLGPLM1 · Prototype