Cores
Open HDL cores for FPGA. License, tests and activity checked on GitHub.
| Core | Maturity | License | Language | Activity |
|---|---|---|---|---|
| Efinix Sapphire RV64 SoC CPUs and compute | M1 · Prototype | No license found | — | — |
| LitePCIe Interfaces and peripherals | M2 · Simulation-tested | No license found | Migen/Python/Verilog | updated 8 days ago |
| BaseJump STL Buses and infrastructure | M2 · Simulation-tested | No license found | — | updated 4 days ago |
| OpenHW CV32E40S CPUs and compute | M2 · Simulation-tested | No license found | — | updated 2 years ago |
| OpenHW CV32E40X CPUs and compute | M2 · Simulation-tested | No license found | — | updated 2 years ago |
| hdl-util HDMI Audio and video | M4 · Production-ready | No license found | Verilog/VHDL | updated 3 months ago |
| OpenRISC or1200 CPUs and compute | M2 · Simulation-tested | No license found | Verilog | updated 11 years ago |
| MiSTer ao486 Retro | M2 · Simulation-tested | No license found | — | updated 15 days ago |
| MiSTer Minimig Retro | M2 · Simulation-tested | No license found | — | updated 15 days ago |
| wb_ram Memory and storage | M1 · Prototype | No license found | — | — |
| cdc_utils Buses and infrastructure | M1 · Prototype | No license found | — | — |
| OpenTitan GPIO IP Buses and infrastructure | M1 · Prototype | No license found | — | — |
| hdl-util VGA Audio and video | M1 · Prototype | No license found | — | — |
| LiteHyperBus Memory and storage | M1 · Prototype | No license found | — | — |
| verilog-spi Interfaces and peripherals | M1 · Prototype | No license found | — | — |
| opencores des core Cryptography | M1 · Prototype | No license found | Verilog/VHDL unknown until review | — |
| opencores jpeg encoder Audio and video | M1 · Prototype | No license found | Verilog/VHDL unknown until review | — |
| opencores sha256 core Cryptography | M1 · Prototype | No license found | Verilog/VHDL unknown until review | — |
| opencores gpio Buses and infrastructure | M1 · Prototype | No license found | Verilog/VHDL unknown until review | — |
| opencores pwm Interfaces and peripherals | M1 · Prototype | No license found | Verilog/VHDL unknown until review | — |
| opencores cordic DSP and radio | M1 · Prototype | No license found | Verilog/VHDL unknown until review | — |
| opencores fft DSP and radio | M1 · Prototype | No license found | Verilog/VHDL unknown until review | — |
| opencores simple spi Interfaces and peripherals | M1 · Prototype | No license found | Verilog/VHDL unknown until review | — |
| OpenCores UART16550 Interfaces and peripherals | M1 · Prototype | No license found | Verilog | — |