Configurable soft RISC-V SoC from Efinix: 1 to 4 64-bit cores, optional SV39 MMU, L1 and L2 caches, DDR3, LPDDR4x and HyperRAM controller for Efinix FPGAs; licence not stated.
CPUs and computeNo license foundM1 · Prototype
Cores
Open HDL cores for FPGA. License, tests and activity checked on GitHub.
LitePCIe
Checked on GitHubOpen PCIe ecosystem core.
Interfaces and peripheralsMigen/Python/VerilogNo license foundM2 · Simulation-testedupdated 8 days ago
BaseJump STL
Checked on GitHubReusable SystemVerilog library.
Buses and infrastructureNo license foundM2 · Simulation-testedupdated 4 days ago
OpenHW CV32E40S
Checked on GitHubSecurity-oriented CORE-V core variant.
CPUs and computeNo license foundM2 · Simulation-testedupdated 2 years ago
OpenHW CV32E40X
Checked on GitHubCORE-V core variant.
CPUs and computeNo license foundM2 · Simulation-testedupdated 2 years ago
hdl-util HDMI
Checked on GitHubOpen HDMI/DVI transmitter candidate.
Audio and videoVerilog/VHDLNo license foundM4 · Production-readyupdated 3 months ago
OpenRISC or1200
Checked on GitHubHistorical open soft CPU baseline.
CPUs and computeVerilogNo license foundM2 · Simulation-testedupdated 11 years ago
MiSTer ao486
Checked on GitHubComplex retro computer core.
RetroNo license foundM2 · Simulation-testedupdated 15 days ago
MiSTer Minimig
Checked on GitHubComputer core example for retro taxonomy.
RetroNo license foundM2 · Simulation-testedupdated 15 days ago
Minimal SoC building block.
Memory and storageNo license foundM1 · Prototype
CDC helpers for composition planner.
Buses and infrastructureNo license foundM1 · Prototype
GPIO reference with register docs.
Buses and infrastructureNo license foundM1 · Prototype
VGA timing core candidate.
Audio and videoNo license foundM1 · Prototype
HyperRAM/HyperFlash ecosystem core.
Memory and storageNo license foundM1 · Prototype
SPI core alternative.
Interfaces and peripheralsNo license foundM1 · Prototype
Risk model example for obsolete crypto.
CryptographyVerilog/VHDL unknown until reviewNo license foundM1 · Prototype
Image processing category seed.
Audio and videoVerilog/VHDL unknown until reviewNo license foundM1 · Prototype
Historical hash core.
CryptographyVerilog/VHDL unknown until reviewNo license foundM1 · Prototype
GPIO category seed.
Buses and infrastructureVerilog/VHDL unknown until reviewNo license foundM1 · Prototype
PWM category seed.
Interfaces and peripheralsVerilog/VHDL unknown until reviewNo license foundM1 · Prototype
CORDIC category seed.
DSP and radioVerilog/VHDL unknown until reviewNo license foundM1 · Prototype
FFT category seed.
DSP and radioVerilog/VHDL unknown until reviewNo license foundM1 · Prototype
Small SPI alternative.
Interfaces and peripheralsVerilog/VHDL unknown until reviewNo license foundM1 · Prototype
Canonical UART reference and common FuseSoC adaptations.
Interfaces and peripheralsVerilogNo license foundM1 · Prototype