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Cores catalog

FPGA/ASIC/HDL/IP cores

An evidence-first catalog for fast engineering triage: reusable value, license risk, verification depth, and board fit before you open the upstream repo.

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How to read cardsA card does not replace upstream docs or license review. Check warnings and commercial-use clarity first, then tests, board evidence, and toolchain fit.Why no featured vendor laneRanking is driven by evidence, review status, and reusable signals. Namespace or vendor identity does not create a privileged lane.
Cores124
P0 launch52
Needs review122
Open flow4
Board linked2

High-risk records in the current index

Submit evidence
P0confidence 2/5

OpenTitan IP blocks

High-quality IP block library with docs and verification culture.

Warning

Manual review is required.

P0confidence 2/5

Ibex

Small open RISC-V CPU used by OpenTitan.

Warning

Manual review is required.

P0confidence 2/5

LiteX

Central open SoC builder and integration framework.

Warning

Manual review is required.

P0confidence 2/5

OpenCores Wishbone

Bus protocol reference for OpenCores-era reusable IP.

Warning

Manual review is required.

P0confidence 2/5

OpenCores WBScope

Useful Wishbone-accessible debug core by ZipCPU author.

Warning

Manual review is required.

Catalog

What is surfacedThe index already surfaces warnings, evidence counts, board links, and review depth. That is enough for triage, but not for a final verdict.25 records
CoreLicense / reviewSignalsInterfaces / flowWarnings
OpenCores Wishbonebus/Wishbone
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.

Bus protocol reference for OpenCores-era reusable IP.

public-domain-like per OpenCores WISHBONE pageLicense riskpublic-domain-like per OpenCores WISHBONE page: HDL/docs/tests/examples still need manual review.M6Maturity levelMaturity M6: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale.
Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale.
SpecificationunknownWishboneunknown
Manual review is required.
OpenCores WBScopeverification/logic analyzer
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.

Useful Wishbone-accessible debug core by ZipCPU author.

GPLLicense riskGPL: HDL/docs/tests/examples still need manual review.M5 candidateMaturity levelMaturity M5 candidate: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale.
Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale.
VerilogJTAG/debugWishboneVerilator
Manual review is required.
OpenCores UART16550peripheral/UART
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.

Canonical UART reference and common FuseSoC adaptations.

unknown until checkedLicense riskunknown until checked: HDL/docs/tests/examples still need manual review.M1-M3 candidateMaturity levelMaturity M1-M3 candidate: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale.
Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale.
VerilogUARTunknownFuseSoC, Verilator
The license requires manual review.The source appears stale or legacy.
OpenCores WDSPDSP/FIR/IIR/FFT
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.

Example of DSP cores with Wishbone and claimed FPGA evidence.

LGPLLicense riskLGPL: HDL/docs/tests/examples still need manual review.M1-M3 candidateMaturity levelMaturity M1-M3 candidate: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale.
Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale.
VHDLunknownWishboneGHDL
The source appears stale or legacy.
IObundle UART16550peripheral/UART
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: github. This is record provenance, not endorsement or quality proof.

Modern adaptation of OpenCores UART16550.

unknownLicense riskunknown: Commercial use is not confirmed.M1-M3 candidateMaturity levelMaturity M1-M3 candidate: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale.
Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale.
unknownUARTunknownunknown
The license requires manual review.
IObundle Ethernetnetwork/Ethernet
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: github. This is record provenance, not endorsement or quality proof.

Ethernet candidate with OpenCores ethmac relation.

unknownLicense riskunknown: Commercial use is not confirmed.M1-M3 candidateMaturity levelMaturity M1-M3 candidate: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale.
Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale.
unknownEthernetunknownunknown
The license requires manual review.
opencores des corecrypto/DES
PriorityP2 review: entry kept for review depth, edge cases, or future ingestion.Review statusReview status: Unreviewed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.

Risk model example for obsolete crypto.

unknownLicense riskunknown: Commercial use is not confirmed.unknownMaturity levelMaturity unknown: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale.
Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale.
Verilog/VHDL unknown until reviewunknownunknownunknown
The license requires manual review.
opencores jpeg encodervideo/image processing
PriorityP2 review: entry kept for review depth, edge cases, or future ingestion.Review statusReview status: Unreviewed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.

Image processing category seed.

unknownLicense riskunknown: Commercial use is not confirmed.unknownMaturity levelMaturity unknown: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale.
Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale.
Verilog/VHDL unknown until reviewunknownunknownunknown
The license requires manual review.
opencores sha256 corecrypto/SHA
PriorityP2 review: entry kept for review depth, edge cases, or future ingestion.Review statusReview status: Unreviewed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.

Historical hash core.

unknownLicense riskunknown: Commercial use is not confirmed.unknownMaturity levelMaturity unknown: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale.
Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale.
Verilog/VHDL unknown until reviewunknownunknownunknown
The license requires manual review.
OpenCores Ethernet MACnetwork/Ethernet
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.

Important comparison point for LiteEth and IObundle Ethernet.

unknownLicense riskunknown: Commercial use is not confirmed.M1-M3 candidateMaturity levelMaturity M1-M3 candidate: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale.
Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale.
VerilogEthernetunknownLiteX, Verilator
The license requires manual review.The source appears stale or legacy.
OpenCores I2C controllerperipheral/I2C
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.

Common small peripheral for beginner/professional comparison.

unknownLicense riskunknown: Commercial use is not confirmed.M1-M3 candidateMaturity levelMaturity M1-M3 candidate: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale.
Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale.
VerilogI2CunknownVerilator
The license requires manual review.The source appears stale or legacy.
OpenCores SPI master/slaveperipheral/SPI
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.

Common reusable peripheral baseline.

unknownLicense riskunknown: Commercial use is not confirmed.M1-M3 candidateMaturity levelMaturity M1-M3 candidate: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale.
Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale.
VerilogSPI/QSPIunknownVerilator
The license requires manual review.The source appears stale or legacy.
opencores gpiosystem/GPIO
PriorityP2 review: entry kept for review depth, edge cases, or future ingestion.Review statusReview status: Unreviewed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.

GPIO category seed.

unknownLicense riskunknown: Commercial use is not confirmed.unknownMaturity levelMaturity unknown: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale.
Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale.
Verilog/VHDL unknown until reviewGPIOunknownunknown
The license requires manual review.Manual review is required.
opencores pwmperipheral/PWM
PriorityP2 review: entry kept for review depth, edge cases, or future ingestion.Review statusReview status: Unreviewed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.

PWM category seed.

unknownLicense riskunknown: Commercial use is not confirmed.unknownMaturity levelMaturity unknown: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale.
Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale.
Verilog/VHDL unknown until reviewPWMunknownunknown
The license requires manual review.Manual review is required.
opencores cordicDSP/CORDIC
PriorityP2 review: entry kept for review depth, edge cases, or future ingestion.Review statusReview status: Unreviewed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.

CORDIC category seed.

unknownLicense riskunknown: Commercial use is not confirmed.unknownMaturity levelMaturity unknown: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale.
Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale.
Verilog/VHDL unknown until reviewunknownunknownunknown
The license requires manual review.Manual review is required.
opencores fftDSP/FFT
PriorityP2 review: entry kept for review depth, edge cases, or future ingestion.Review statusReview status: Unreviewed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.

FFT category seed.

unknownLicense riskunknown: Commercial use is not confirmed.unknownMaturity levelMaturity unknown: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale.
Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale.
Verilog/VHDL unknown until reviewunknownunknownunknown
The license requires manual review.Manual review is required.
opencores simple spiperipheral/SPI
PriorityP2 review: entry kept for review depth, edge cases, or future ingestion.Review statusReview status: Unreviewed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.

Small SPI alternative.

unknownLicense riskunknown: Commercial use is not confirmed.unknownMaturity levelMaturity unknown: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale.
Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale.
Verilog/VHDL unknown until reviewSPI/QSPIunknownunknown
The license requires manual review.Manual review is required.
opencores aes corecrypto/AES
PriorityP2 review: entry kept for review depth, edge cases, or future ingestion.Review statusReview status: Unreviewed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.

Historical AES core to compare with OpenTitan AES.

unknownLicense riskunknown: Commercial use is not confirmed.unknownMaturity levelMaturity unknown: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale.
Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale.
Verilog/VHDL unknown until reviewunknownunknownunknown
The license requires manual review.The source appears stale or legacy.
opencores can coreperipheral/CAN
PriorityP2 review: entry kept for review depth, edge cases, or future ingestion.Review statusReview status: Unreviewed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.

CAN/LIN category seed.

unknownLicense riskunknown: Commercial use is not confirmed.unknownMaturity levelMaturity unknown: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale.
Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale.
Verilog/VHDL unknown until reviewunknownunknownunknown
The license requires manual review.The source appears stale or legacy.
opencores ddr controllermemory/DDR
PriorityP2 review: entry kept for review depth, edge cases, or future ingestion.Review statusReview status: Unreviewed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.

DDR risk-model example.

unknownLicense riskunknown: Commercial use is not confirmed.unknownMaturity levelMaturity unknown: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale.
Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale.
Verilog/VHDL unknown until reviewMemoryunknownunknown
The license requires manual review.The source appears stale or legacy.
opencores sdram controllermemory/SDRAM
PriorityP2 review: entry kept for review depth, edge cases, or future ingestion.Review statusReview status: Unreviewed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.

Memory controller comparison.

unknownLicense riskunknown: Commercial use is not confirmed.unknownMaturity levelMaturity unknown: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale.
Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale.
Verilog/VHDL unknown until reviewMemoryunknownunknown
The license requires manual review.The source appears stale or legacy.
opencores usbhostslaveperipheral/USB
PriorityP2 review: entry kept for review depth, edge cases, or future ingestion.Review statusReview status: Unreviewed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.

USB category seed.

unknownLicense riskunknown: Commercial use is not confirmed.unknownMaturity levelMaturity unknown: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale.
Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale.
Verilog/VHDL unknown until reviewunknownunknownunknown
The license requires manual review.The source appears stale or legacy.
opencores vga lcdvideo/VGA/LCD
PriorityP2 review: entry kept for review depth, edge cases, or future ingestion.Review statusReview status: Unreviewed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.

Video category seed.

unknownLicense riskunknown: Commercial use is not confirmed.unknownMaturity levelMaturity unknown: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale.
Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale.
Verilog/VHDL unknown until reviewVGA/HDMIunknownunknown
The license requires manual review.The source appears stale or legacy.
OpenCores projects directorydirectory
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.

Historical baseline and category source.

unknownLicense riskunknown: Commercial use is not confirmed.M1-M3 candidateMaturity levelMaturity M1-M3 candidate: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale.
Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale.
Verilog/VHDL unknown until reviewunknownunknownunknown
The license requires manual review.The source appears stale or legacy.
opencores minsocSoC/OpenRISC
PriorityP2 review: entry kept for review depth, edge cases, or future ingestion.Review statusReview status: Unreviewed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.

Historical SoC integration reference.

unknownLicense riskunknown: Commercial use is not confirmed.unknownMaturity levelMaturity unknown: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale.
Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale.
Verilog/VHDL unknown until reviewunknownunknownunknown
The license requires manual review.The source appears stale or legacy.