P0confidence 2/5
OpenTitan IP blocks
High-quality IP block library with docs and verification culture.
Manual review is required.
Cores catalog
FPGA/ASIC/HDL/IP cores
An evidence-first catalog for fast engineering triage: reusable value, license risk, verification depth, and board fit before you open the upstream repo.
How to read cardsA card does not replace upstream docs or license review. Check warnings and commercial-use clarity first, then tests, board evidence, and toolchain fit.Why no featured vendor laneRanking is driven by evidence, review status, and reusable signals. Namespace or vendor identity does not create a privileged lane.
Cores124
P0 launch52
Needs review122
Open flow4
Board linked2
High-risk records in the current index
Submit evidenceP0confidence 2/5
Ibex
Small open RISC-V CPU used by OpenTitan.
Manual review is required.
P0confidence 2/5
LiteX
Central open SoC builder and integration framework.
Manual review is required.
P0confidence 2/5
OpenCores Wishbone
Bus protocol reference for OpenCores-era reusable IP.
Manual review is required.
P0confidence 2/5
OpenCores WBScope
Useful Wishbone-accessible debug core by ZipCPU author.
Manual review is required.
Catalog
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.
OpenCores Wishbone
bus/Wishbone
Manual review is required.
Bus protocol reference for OpenCores-era reusable IP.
Licensepublic-domain-like per OpenCores WISHBONE pageLicense riskpublic-domain-like per OpenCores WISHBONE page: HDL/docs/tests/examples still need manual review.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q54
Use54
Int52
Ver18
Specificationpublic-domain-like per OpenCores WISHBONE pageunknownWishbone
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.
OpenCores WBScope
verification/logic analyzer
Manual review is required.
Useful Wishbone-accessible debug core by ZipCPU author.
LicenseGPLLicense riskGPL: HDL/docs/tests/examples still need manual review.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q54
Use72
Int52
Ver40
VerilogGPLJTAG/debugWishbone
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.
OpenCores WDSP
DSP/FIR/IIR/FFT
The source appears stale or legacy.
Example of DSP cores with Wishbone and claimed FPGA evidence.
LicenseLGPLLicense riskLGPL: HDL/docs/tests/examples still need manual review.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q48
Use54
Int52
Ver22
VHDLLGPLunknownWishbone
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: github. This is record provenance, not endorsement or quality proof.
ZipCPU
processor/soft CPU
The license requires manual review.
CPU, Wishbone and formal-heavy ecosystem.
LicenseunknownLicense riskunknown: Commercial use is not confirmed.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use72
Int52
Ver40
VerilogunknownWishbone
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: github. This is record provenance, not endorsement or quality proof.
ZipCPU wb2axip
bus bridge/formal
The license requires manual review.
Wishbone/AXI bridge and formal property library.
LicenseunknownLicense riskunknown: Commercial use is not confirmed.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use72
Int52
Ver40
VerilogunknownWishboneAXI
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: github. This is record provenance, not endorsement or quality proof.
wb_bfm
verification/Wishbone BFM
The license requires manual review.
Verification helper for Wishbone cores.
LicenseunknownLicense riskunknown: Commercial use is not confirmed.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use54
Int52
Ver40
unknownWishbone
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: github. This is record provenance, not endorsement or quality proof.
wb_intercon
bus/Wishbone interconnect
The license requires manual review.
Common Wishbone interconnect package.
LicenseunknownLicense riskunknown: Commercial use is not confirmed.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use72
Int52
Ver40
unknownWishbone
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: github. This is record provenance, not endorsement or quality proof.
wb_ram
memory/Wishbone RAM
The license requires manual review.
Minimal SoC building block.
LicenseunknownLicense riskunknown: Commercial use is not confirmed.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use54
Int52
Ver40
unknownMemoryWishbone
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: github. This is record provenance, not endorsement or quality proof.
OpenRISC mor1kx
processor/OpenRISC
The license requires manual review.
The source appears stale or legacy.
OpenRISC core relevant to Wishbone history.
LicenseunknownLicense riskunknown: Commercial use is not confirmed.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use54
Int52
Ver22
VerilogunknownWishbone