P0confidence 2/5
OpenTitan IP blocks
High-quality IP block library with docs and verification culture.
Manual review is required.
Cores catalog
FPGA/ASIC/HDL/IP cores
An evidence-first catalog for fast engineering triage: reusable value, license risk, verification depth, and board fit before you open the upstream repo.
How to read cardsA card does not replace upstream docs or license review. Check warnings and commercial-use clarity first, then tests, board evidence, and toolchain fit.Why no featured vendor laneRanking is driven by evidence, review status, and reusable signals. Namespace or vendor identity does not create a privileged lane.
Cores124
P0 launch52
Needs review122
Open flow4
Board linked2
High-risk records in the current index
Submit evidenceP0confidence 2/5
Ibex
Small open RISC-V CPU used by OpenTitan.
Manual review is required.
P0confidence 2/5
LiteX
Central open SoC builder and integration framework.
Manual review is required.
P0confidence 2/5
OpenCores Wishbone
Bus protocol reference for OpenCores-era reusable IP.
Manual review is required.
P0confidence 2/5
OpenCores WBScope
Useful Wishbone-accessible debug core by ZipCPU author.
Manual review is required.
Catalog
| Core | License / review | Signals | Interfaces / flow | Warnings |
|---|---|---|---|---|
OpenCores Wishbonebus/Wishbone PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof. Bus protocol reference for OpenCores-era reusable IP. | public-domain-like per OpenCores WISHBONE pageLicense riskpublic-domain-like per OpenCores WISHBONE page: HDL/docs/tests/examples still need manual review.M6Maturity levelMaturity M6: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale. | Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale. | SpecificationunknownWishboneunknown | Manual review is required. |
OpenCores WBScopeverification/logic analyzer PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof. Useful Wishbone-accessible debug core by ZipCPU author. | GPLLicense riskGPL: HDL/docs/tests/examples still need manual review.M5 candidateMaturity levelMaturity M5 candidate: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale. | Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale. | VerilogJTAG/debugWishboneVerilator | Manual review is required. |
OpenCores WDSPDSP/FIR/IIR/FFT PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof. Example of DSP cores with Wishbone and claimed FPGA evidence. | LGPLLicense riskLGPL: HDL/docs/tests/examples still need manual review.M1-M3 candidateMaturity levelMaturity M1-M3 candidate: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale. | Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale. | VHDLunknownWishboneGHDL | The source appears stale or legacy. |
ZipCPUprocessor/soft CPU PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: github. This is record provenance, not endorsement or quality proof. CPU, Wishbone and formal-heavy ecosystem. | unknownLicense riskunknown: Commercial use is not confirmed.M1-M3 candidateMaturity levelMaturity M1-M3 candidate: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale. | Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale. | VerilogunknownWishboneVerilator | The license requires manual review. |
ZipCPU wb2axipbus bridge/formal PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: github. This is record provenance, not endorsement or quality proof. Wishbone/AXI bridge and formal property library. | unknownLicense riskunknown: Commercial use is not confirmed.M1-M3 candidateMaturity levelMaturity M1-M3 candidate: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale. | Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale. | VerilogunknownWishbone, AXIVerilator | The license requires manual review. |
wb_bfmverification/Wishbone BFM PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: github. This is record provenance, not endorsement or quality proof. Verification helper for Wishbone cores. | unknownLicense riskunknown: Commercial use is not confirmed.M1-M3 candidateMaturity levelMaturity M1-M3 candidate: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale. | Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale. | unknownunknownWishboneunknown | The license requires manual review. |
wb_interconbus/Wishbone interconnect PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: github. This is record provenance, not endorsement or quality proof. Common Wishbone interconnect package. | unknownLicense riskunknown: Commercial use is not confirmed.M1-M3 candidateMaturity levelMaturity M1-M3 candidate: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale. | Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale. | unknownunknownWishboneunknown | The license requires manual review. |
wb_rammemory/Wishbone RAM PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: github. This is record provenance, not endorsement or quality proof. Minimal SoC building block. | unknownLicense riskunknown: Commercial use is not confirmed.M1-M3 candidateMaturity levelMaturity M1-M3 candidate: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale. | Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale. | unknownMemoryWishboneunknown | The license requires manual review. |
OpenRISC mor1kxprocessor/OpenRISC PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: github. This is record provenance, not endorsement or quality proof. OpenRISC core relevant to Wishbone history. | unknownLicense riskunknown: Commercial use is not confirmed.M1-M3 candidateMaturity levelMaturity M1-M3 candidate: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale. | Q / Int / VerQuality / Integration / VerificationEvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records.ConfidenceReview/evidence confidence on a five-point scale. | VerilogunknownWishboneVerilator | The license requires manual review.The source appears stale or legacy. |