The practical FPGA flow is lint/simulation, synthesis, constraints, place-and-route, timing, bitstream, programming and board validation.
flowsynthesispnrbitstream
Knowledge base
Engineering FPGA knowledge base
Articles are linked to boards, chips, toolchains, sources and warnings.
Results
Most beginner failures come from missing constraints, misunderstood clocks, latch inference, multiple drivers, skipped simulation and wrong board variant.
debugbeginnerpitfalls
A minimal simulation has a DUT, testbench, clock/reset generation, stimulus, assertions or checks, and waveform capture only when needed.
simulationverilogtestbench
Verilator compiles synthesizable Verilog/SystemVerilog into C++ or SystemC models for fast simulation and linting.
verilatorsimulationlint
GHDL is an open-source VHDL simulator and synthesis-related tool used in VHDL verification and open FPGA flows.
ghdlvhdlsimulation
cocotb lets Python testbenches drive HDL simulators, which is useful for protocol tests, scoreboards and integration-style verification.
cocotbverificationsimulation
Formal verification proves properties over all possible inputs within a bounded or inductive model instead of checking selected simulation traces.
formalsbyassertions
Glossary
FPGA
Field-programmable gate array: configurable digital logic fabric programmed after manufacturing.
CPLD
Programmable logic device usually smaller and more deterministic than an FPGA.
LUT
Look-up table used as a basic FPGA logic element.
Flip-flop
Sequential storage element usually clocked by a clock edge.
BRAM
Dedicated block memory inside FPGA fabric.
DSP block
Dedicated arithmetic block for operations such as multiplication and accumulation.
PLL
Clock management block used to generate or condition clocks.
Bitstream
Configuration data loaded into an FPGA to realize a design.
Synthesis
Conversion of HDL into a gate-level or technology-mapped representation.
Place-and-route
Mapping logic to physical locations and routing signals between them.
Static timing analysis
Timing analysis that checks paths against constraints without dynamic simulation.
Slack
Timing margin between required and actual path timing.
CDC
Clock domain crossing; transfer of signals between different clock domains.
Metastability
Unstable state of a sequential element when setup or hold assumptions are violated.
Constraint file
File describing pin assignments, clocks, I/O standards and timing constraints.
XDC
AMD/Xilinx Design Constraints format used by Vivado.
SDC
Synopsys Design Constraints format used by multiple FPGA tools.
PCF
Physical constraints format commonly seen in open iCE40 flows.
QSF
Quartus Settings File used in Intel FPGA projects.
CST
Constraint format used in Gowin FPGA projects.
Pmod
Small expansion connector ecosystem popular on educational FPGA boards.
FMC
FPGA Mezzanine Card connector standard for expansion modules.
JTAG
Debug and programming interface used by many FPGA boards.
UART
Asynchronous serial interface often used for simple board debug.
SPI
Synchronous serial interface commonly used for flash and peripheral chips.
I2C
Two-wire serial bus often used for low-speed control devices.
AXI
AMBA interconnect protocol family widely used in SoC FPGA designs.
Wishbone
Open interconnect bus used in many open-source FPGA SoC projects.
Softcore CPU
Processor implemented in FPGA fabric rather than as hardened silicon.
RAG
Retrieval-augmented generation; answering with retrieved source-backed context.