P0confidence 2/5
OpenTitan IP blocks
High-quality IP block library with docs and verification culture.
Manual review is required.
Cores catalog
FPGA/ASIC/HDL/IP cores
An evidence-first catalog for fast engineering triage: reusable value, license risk, verification depth, and board fit before you open the upstream repo.
How to read cardsA card does not replace upstream docs or license review. Check warnings and commercial-use clarity first, then tests, board evidence, and toolchain fit.Why no featured vendor laneRanking is driven by evidence, review status, and reusable signals. Namespace or vendor identity does not create a privileged lane.
Cores124
P0 launch52
Needs review122
Open flow4
Board linked2
High-risk records in the current index
Submit evidenceP0confidence 2/5
Ibex
Small open RISC-V CPU used by OpenTitan.
Manual review is required.
P0confidence 2/5
LiteX
Central open SoC builder and integration framework.
Manual review is required.
P0confidence 2/5
OpenCores Wishbone
Bus protocol reference for OpenCores-era reusable IP.
Manual review is required.
P0confidence 2/5
OpenCores WBScope
Useful Wishbone-accessible debug core by ZipCPU author.
Manual review is required.
Catalog
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: github. This is record provenance, not endorsement or quality proof.
LiteX
SoC builder/generator
Manual review is required.
Central open SoC builder and integration framework.
LicenseBSD-2-Clause-like until checkedLicense riskBSD-2-Clause-like until checked: Current metadata does not show an explicit license blocker.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q54
Use72
Int52
Ver40
Migen/Python/VerilogBSD-2-Clause-like until checkedMemory
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: github. This is record provenance, not endorsement or quality proof.
LiteDRAM
memory/DRAM
The license requires manual review.
Open DRAM controller ecosystem used with LiteX.
LicenseunknownLicense riskunknown: Commercial use is not confirmed.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use72
Int76
Ver40
Migen/Python/VerilogunknownMemory
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: github. This is record provenance, not endorsement or quality proof.
fifo
memory/FIFO
The license requires manual review.
Generic FIFO baseline.
LicenseunknownLicense riskunknown: Commercial use is not confirmed.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use54
Int52
Ver40
unknownFIFO/streamMemory
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: github. This is record provenance, not endorsement or quality proof.
IObundle cache
memory/cache
The license requires manual review.
Open cache candidate.
LicenseunknownLicense riskunknown: Commercial use is not confirmed.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use54
Int52
Ver40
unknownMemory
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: github. This is record provenance, not endorsement or quality proof.
wb_ram
memory/Wishbone RAM
The license requires manual review.
Minimal SoC building block.
LicenseunknownLicense riskunknown: Commercial use is not confirmed.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use54
Int52
Ver40
unknownMemoryWishbone
PriorityP1 expansion: useful candidate after the baseline P0 set.Review statusReview status: Unreviewed. Manual review is still required beyond seed/index metadata.Source typeSource type: github. This is record provenance, not endorsement or quality proof.
LiteHyperBus
memory/HyperBus
The license requires manual review.
HyperRAM/HyperFlash ecosystem core.
LicenseunknownLicense riskunknown: Commercial use is not confirmed.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use54
Int49
Ver37
unknownMemory