P0confidence 2/5
OpenTitan IP blocks
High-quality IP block library with docs and verification culture.
Manual review is required.
Cores catalog
FPGA/ASIC/HDL/IP cores
An evidence-first catalog for fast engineering triage: reusable value, license risk, verification depth, and board fit before you open the upstream repo.
How to read cardsA card does not replace upstream docs or license review. Check warnings and commercial-use clarity first, then tests, board evidence, and toolchain fit.Why no featured vendor laneRanking is driven by evidence, review status, and reusable signals. Namespace or vendor identity does not create a privileged lane.
Cores124
P0 launch52
Needs review122
Open flow4
Board linked2
High-risk records in the current index
Submit evidenceP0confidence 2/5
Ibex
Small open RISC-V CPU used by OpenTitan.
Manual review is required.
P0confidence 2/5
LiteX
Central open SoC builder and integration framework.
Manual review is required.
P0confidence 2/5
OpenCores Wishbone
Bus protocol reference for OpenCores-era reusable IP.
Manual review is required.
P0confidence 2/5
OpenCores WBScope
Useful Wishbone-accessible debug core by ZipCPU author.
Manual review is required.
Catalog
P0Auto indexedgithub
OpenTitan IP blocks
security/root-of-trust/IP blocks
High-quality IP block library with docs and verification culture.
LicenseApache-2.0Lower commercial risk
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q54
Use72
Int52
Ver40
SystemVerilogApache-2.0unknown
Manual review is required.
P0Auto indexedgithub
Ibex
processor/RISC-V
Small open RISC-V CPU used by OpenTitan.
LicenseApache-2.0Lower commercial risk
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q54
Use72
Int52
Ver40
SystemVerilogApache-2.0unknown
Manual review is required.
P0Auto indexedgithub
LiteX
SoC builder/generator
Central open SoC builder and integration framework.
LicenseBSD-2-Clause-like until checkedLower commercial risk
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q54
Use72
Int52
Ver40
Migen/Python/VerilogBSD-2-Clause-like until checkedMemory
Manual review is required.
P2Manually reviewedgithub
AccelFury core-template
generator / template / IP methodology
Шаблон production-style FPGA IP: manifest, registry, board/toolchain scaffolding, SPDX checks, separated licenses and release checklist.
LicenseCERN-OHL-S-2.0 + AGPL + CC-BY-SALicense needs review
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q42
Use36
Int70
Ver18
Rust/SystemVerilog/TypeScriptCERN-OHL-S-2.0 + AGPL + CC-BY-SAunknown
This is a template/example, not a standalone core.
Generated projects require separate review.
P0Auto indexedgithub
OpenHW CORE-V cores
processor/RISC-V
Industrial-grade open RISC-V core family source.
LicenseSolderpadLicense needs review
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q54
Use72
Int52
Ver40
SystemVerilogSolderpadunknown
Manual review is required.
P0Auto indexedgithub
jotego jtcores
retro/arcade
Large curated arcade FPGA core ecosystem.
LicenseGPL-3.0License needs review
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q54
Use72
Int52
Ver40
VerilogGPL-3.0unknown
There is legal risk around ROM/retro assets.
P1Manually reviewedgithub
AccelFury af-pdm-rx
audio / sensor interface / PDM RX
Raw PDM RX core на Verilog-2001 для MEMS microphones: генерирует PDM clock, сэмплирует 1-битный поток и выдаёт valid/ready stream. Не выполняет PDM-to-PCM decimation.
LicenseAccelFury Source AvailableSource-available limitation
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q48
Use72
Int49
Ver37
Verilog-2001AccelFury Source AvailablePDM
Source is available, but commercial use may require a separate license.
The core does not include a decimator/CIC/FIR pipeline.
P0Auto indexedgithub
SERV
processor/RISC-V/tiny
Tiny RISC-V core and FuseSoC-friendly ecosystem.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use72
Int76
Ver40
Verilogunknown
The license requires manual review.
P1Unreviewedgithub
OpenHW CV32E40P
processor/RISC-V
Specific CORE-V core with verification evidence.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use72
Int49
Ver37
SystemVerilogunknown
The license requires manual review.
P0Auto indexedgithub
CORE-V-VERIF
verification/RISC-V
Verification evidence model for CORE-V cores.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use72
Int52
Ver40
SystemVerilog/UVMunknown
The license requires manual review.
P0Auto indexedgithub
Open Logic AXI/base/intf
library/interfaces/math
FuseSoC-listed open logic package family.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use54
Int76
Ver40
unknownAXI
The license requires manual review.
P0Auto indexedgithub
ZipCPU
processor/soft CPU
CPU, Wishbone and formal-heavy ecosystem.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use72
Int52
Ver40
VerilogunknownWishbone
The license requires manual review.
P0Auto indexedgithub
ZipCPU wb2axip
bus bridge/formal
Wishbone/AXI bridge and formal property library.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use72
Int52
Ver40
VerilogunknownWishboneAXI
The license requires manual review.
P0Auto indexedgithub
LiteDRAM
memory/DRAM
Open DRAM controller ecosystem used with LiteX.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use72
Int76
Ver40
Migen/Python/VerilogunknownMemory
The license requires manual review.
P0Auto indexedgithub
VexRiscv
processor/RISC-V/generator
Configurable RISC-V softcore used in LiteX ecosystem.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use72
Int76
Ver40
SpinalHDL/Scala/Verilogunknown
The license requires manual review.
P0Auto indexedgithub
wb_bfm
verification/Wishbone BFM
Verification helper for Wishbone cores.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use54
Int52
Ver40
unknownWishbone
The license requires manual review.
P0Auto indexedgithub
LiteSATA
storage/SATA
High-value storage/networked design reference.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use54
Int52
Ver40
Migen/Python/VerilogunknownSATA
The license requires manual review.
P0Auto indexedgithub
LiteSPI
peripheral/SPI flash
Common SPI/SPI flash block in LiteX designs.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use54
Int76
Ver40
Migen/Python/VerilogunknownSPI/QSPI
The license requires manual review.
P0Auto indexedgithub
YosysHQ sby
formal/tooling
Formal verification flow signal.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use54
Int52
Ver18
unknown
The license requires manual review.
This is not confirmed to be a reusable RTL core.
P0Auto indexedgithub
Amaranth HDL
generator/Amaranth
Modern Python-based HDL ecosystem source.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use72
Int52
Ver40
unknown
The license requires manual review.
P0Auto indexedgithub
LiteEth
network/Ethernet
Modern Ethernet core comparison point.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use72
Int52
Ver40
Migen/Python/VerilogunknownEthernet
The license requires manual review.
P0Auto indexedgithub
NEORV32
processor/RISC-V/SoC
Well-documented VHDL RISC-V SoC candidate.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use72
Int52
Ver40
VHDLunknown
The license requires manual review.
P0Auto indexedgithub
PicoRV32
processor/RISC-V
Compact softcore with strong FPGA relevance.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use72
Int52
Ver40
Verilogunknown
The license requires manual review.
P0Auto indexedgithub
pulp-platform axi
bus/AXI
AXI components and infrastructure.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use72
Int52
Ver40
SystemVerilogunknownAXI
The license requires manual review.
P0Auto indexedgithub
pulp-platform common_cells
library/SystemVerilog cells
Reusable cells widely used by PULP projects.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use72
Int52
Ver40
SystemVerilogunknown
The license requires manual review.
P0Auto indexedgithub
pulp-platform cva6
processor/RISC-V
Linux-capable RISC-V core lineage.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use72
Int52
Ver40
SystemVerilogunknown
The license requires manual review.
P0Auto indexedgithub
wb_intercon
bus/Wishbone interconnect
Common Wishbone interconnect package.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use72
Int52
Ver40
unknownWishbone
The license requires manual review.
P0Auto indexedgithub
fifo
memory/FIFO
Generic FIFO baseline.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use54
Int52
Ver40
unknownFIFO/streamMemory
The license requires manual review.
P0Auto indexedgithub
IObundle UART16550
peripheral/UART
Modern adaptation of OpenCores UART16550.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use54
Int52
Ver40
unknownUART
The license requires manual review.
P0Auto indexedgithub
uart verilog by alexforencich
peripheral/UART
Common GitHub UART implementation.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use54
Int52
Ver40
unknownUART
The license requires manual review.
P0Auto indexedgithub
cdc_utils
CDC utilities
CDC helpers for composition planner.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use54
Int52
Ver40
unknown
The license requires manual review.
P0Auto indexedgithub
IObundle cache
memory/cache
Open cache candidate.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use54
Int52
Ver40
unknownMemory
The license requires manual review.
P0Auto indexedgithub
IObundle Ethernet
network/Ethernet
Ethernet candidate with OpenCores ethmac relation.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use54
Int52
Ver40
unknownEthernet
The license requires manual review.
P0Auto indexedgithub
jotego JT12
audio/FM synthesis
FM sound core useful for retro/audio category.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use54
Int52
Ver40
Verilogunknown
The license requires manual review.
P0Auto indexedgithub
LiteScope
debug/logic analyzer
Debug infrastructure for composition planner.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use54
Int52
Ver40
Migen/Python/VerilogunknownJTAG/debug
The license requires manual review.
P0Auto indexedgithub
LiteSDCard
storage/SDCard
Useful storage peripheral for SoC designs.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use54
Int52
Ver40
Migen/Python/VerilogunknownSD/SDIO
The license requires manual review.
P0Auto indexedgithub
stream_utils
stream utilities
Stream FIFO/width conversion baseline.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use54
Int52
Ver40
unknownFIFO/stream
The license requires manual review.
P0Auto indexedgithub
Wally RISC-V
processor/RISC-V
Open RISC-V core family for comparison.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use54
Int52
Ver40
SystemVerilogunknown
The license requires manual review.
P0Auto indexedgithub
wb_ram
memory/Wishbone RAM
Minimal SoC building block.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use54
Int52
Ver40
unknownMemoryWishbone
The license requires manual review.
P1Unreviewedgithub
Project F FPGA graphics
video/education
Good KB reference for graphics pipelines.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use54
Int49
Ver37
unknown
The license requires manual review.
P0Auto indexedgithub
OpenRISC or1200
processor/OpenRISC
Historical open soft CPU baseline.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use54
Int52
Ver40
Verilogunknown
The license requires manual review.
Manual review is required.
P0Auto indexedgithub
LitePCIe
peripheral/PCIe
Open PCIe ecosystem core.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use72
Int52
Ver40
Migen/Python/VerilogunknownPCIe
The license requires manual review.
There is a vendor tooling or license constraint.
P1Unreviewedgithub
LambdaConcept LiteICLink
SerDes/inter-chip
LiteX complex link core.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use54
Int73
Ver37
unknown
The license requires manual review.
P1Unreviewedgithub
F4PGA
toolchain/open FPGA flow
Open flow support signal.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use54
Int49
Ver37
unknown
The license requires manual review.
P1Unreviewedgithub
Caliptra RTL
security/root-of-trust
CHIPS Alliance root-of-trust IP.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use72
Int49
Ver37
unknown
The license requires manual review.
P1Unreviewedgithub
Rocket Chip
processor/RISC-V/generator
Important Chisel generator ecosystem.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use72
Int49
Ver37
unknown
The license requires manual review.
P1Unreviewedgithub
verilog-axi
bus/AXI
AXI component library and comparison source.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use72
Int49
Ver37
unknownAXI
The license requires manual review.
P1Unreviewedgithub
verilog-ethernet
network/Ethernet
Ethernet MAC/UDP/IP stack candidate.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use72
Int49
Ver37
unknownEthernet
The license requires manual review.
P0Auto indexedgithub
YosysHQ nextpnr
toolchain/place-and-route
Open P&R support signal.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use54
Int52
Ver18
unknown
The license requires manual review.
This is not confirmed to be a reusable RTL core.
P0Auto indexedgithub
YosysHQ yosys
toolchain/synthesis
Open synthesis toolchain for support matrix.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use54
Int52
Ver18
unknown
The license requires manual review.
This is not confirmed to be a reusable RTL core.
P1Unreviewedgithub
Amaranth stdlib
generator/stdlib
Amaranth ecosystem discovery root.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use54
Int49
Ver37
unknown
The license requires manual review.
P1Unreviewedgithub
BaseJump STL
library/SystemVerilog
Reusable SystemVerilog library.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use54
Int49
Ver37
unknown
The license requires manual review.
P1Unreviewedgithub
Berkeley HardFloat
math/floating point
Floating-point arithmetic core family.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use54
Int49
Ver37
unknown
The license requires manual review.
P1Unreviewedgithub
BlackParrot
processor/RISC-V manycore
Manycore RISC-V candidate.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use54
Int49
Ver37
unknown
The license requires manual review.
P1Unreviewedgithub
BOOM
processor/RISC-V OoO
High-end RISC-V research core.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use54
Int49
Ver37
unknown
The license requires manual review.
P1Unreviewedgithub
hdl-util VGA
video/VGA
VGA timing core candidate.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use54
Int49
Ver37
unknownVGA/HDMI
The license requires manual review.
P1Unreviewedgithub
jt51
audio/FM synthesis
YM2151 clone candidate.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use54
Int49
Ver37
unknown
The license requires manual review.
P1Unreviewedgithub
jtopl
audio/FM synthesis
OPL-compatible sound core candidate.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use54
Int49
Ver37
unknown
The license requires manual review.
P1Unreviewedgithub
LiteHyperBus
memory/HyperBus
HyperRAM/HyperFlash ecosystem core.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use54
Int49
Ver37
unknownMemory
The license requires manual review.
P1Unreviewedgithub
LiteJESD204B
converter/JESD204B
JESD204B open core candidate.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use54
Int49
Ver37
unknown
The license requires manual review.
P1Unreviewedgithub
OpenHW CV32E40S
processor/RISC-V/security
Security-oriented CORE-V core variant.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use54
Int49
Ver37
unknown
The license requires manual review.
P1Unreviewedgithub
OpenHW CV32E40X
processor/RISC-V
CORE-V core variant.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use54
Int49
Ver37
unknown
The license requires manual review.
P1Unreviewedgithub
Project F display controller
video/display
Clear video/display learning resource.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use54
Int49
Ver37
unknownVGA/HDMI
The license requires manual review.
P1Unreviewedgithub
taxi
bus/AXI/stream
Successor ecosystem for AXI/stream components.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use54
Int49
Ver37
unknownFIFO/streamAXI
The license requires manual review.
P1Unreviewedgithub
ultraembedded core_soc
SoC/RISC-V
SoC integration candidate.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use54
Int49
Ver37
unknown
The license requires manual review.
P1Unreviewedgithub
ultraembedded riscv
processor/RISC-V
RISC-V core comparison source.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use54
Int49
Ver37
unknown
The license requires manual review.
P1Unreviewedgithub
verilog-i2c
peripheral/I2C
I2C core alternative.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use54
Int49
Ver37
unknownI2C
The license requires manual review.
P1Unreviewedgithub
verilog-spi
peripheral/SPI
SPI core alternative.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use54
Int49
Ver37
unknownSPI/QSPI
The license requires manual review.
P0Auto indexedgithub
OpenRISC mor1kx
processor/OpenRISC
OpenRISC core relevant to Wishbone history.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use54
Int52
Ver22
VerilogunknownWishbone
The license requires manual review.
The source appears stale or legacy.
P1Unreviewedgithub
verilog-pcie
peripheral/PCIe
PCIe endpoint/DMA candidate.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use54
Int49
Ver37
unknownPCIe
The license requires manual review.
There is a vendor tooling or license constraint.
P0Auto indexedgithub
MiSTer-devel organization
retro/platform
Central MiSTer ecosystem source.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q46
Use72
Int52
Ver40
unknown
The license requires manual review.
There is legal risk around ROM/retro assets.
P1Unreviewedgithub
hdl-util HDMI
video/HDMI
Open HDMI/DVI transmitter candidate.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use72
Int49
Ver37
Verilog/VHDLunknownVGA/HDMI
The license requires manual review.
There is a vendor tooling or license constraint.
P1Unreviewedgithub
verilog-axis
bus/AXI-Stream
AXI-Stream component library.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use72
Int49
Ver37
unknownFIFO/streamAXI
The license requires manual review.
P1Unreviewedgithub
Verible
tooling/lint/format
Lint/style evidence tool.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use54
Int49
Ver18
unknown
The license requires manual review.
This is not confirmed to be a reusable RTL core.
P1Unreviewedgithub
FPGA Interchange
tooling/interchange
Toolchain interoperability source.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use36
Int49
Ver18
unknown
The license requires manual review.
This is not confirmed to be a reusable RTL core.
P1Unreviewedgithub
Surelog
tooling/SystemVerilog parser
SystemVerilog parsing support signal.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use36
Int49
Ver18
unknown
The license requires manual review.
This is not confirmed to be a reusable RTL core.
P1Unreviewedgithub
UHDM
tooling/SystemVerilog data model
SV tooling ecosystem source.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use36
Int49
Ver18
unknown
The license requires manual review.
This is not confirmed to be a reusable RTL core.
P1Unreviewedgithub
MiSTer ao486
retro/computer/x86
Complex retro computer core.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use54
Int49
Ver37
unknown
The license requires manual review.
There is legal risk around ROM/retro assets.
P1Unreviewedgithub
MiSTer Minimig
retro/computer
Computer core example for retro taxonomy.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use54
Int49
Ver37
unknown
The license requires manual review.
There is legal risk around ROM/retro assets.
P1Unreviewedgithub
MiSTer NES
retro/console
Console core example.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use54
Int49
Ver37
unknown
The license requires manual review.
There is legal risk around ROM/retro assets.
P1Unreviewedgithub
MiSTer SNES
retro/console
Console core example.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use54
Int49
Ver37
unknown
The license requires manual review.
There is legal risk around ROM/retro assets.
P1Unreviewedgithub
MiSTer Main_MiSTer
retro/platform
MiSTer platform integration source.
LicenseunknownNo clear license
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q40
Use36
Int49
Ver18
unknown
The license requires manual review.
There is legal risk around ROM/retro assets.