Cores
Open HDL cores for FPGA. License, tests and activity checked on GitHub.
| Core | Maturity | License | Language | Activity |
|---|---|---|---|---|
| OpenTitan UART IP Interfaces and peripherals | M4 · Production-ready | Apache-2.0 | — | updated today |
| OpenTitan I2C IP Interfaces and peripherals | M4 · Production-ready | Apache-2.0 | — | updated today |
| OpenTitan SPI device IP Interfaces and peripherals | M4 · Production-ready | Apache-2.0 | — | updated today |
| uart verilog by alexforencich Interfaces and peripherals | M2 · Simulation-tested | MIT | — | updated 2 years ago |
| LiteSPI Interfaces and peripherals | M2 · Simulation-tested | BSD-2-Clause | Migen/Python/Verilog | updated 8 days ago |
| verilog-ethernet Interfaces and peripherals | M2 · Simulation-tested | MIT | — | updated 2 years ago |
| verilog-i2c Interfaces and peripherals | M2 · Simulation-tested | MIT | — | updated 2 years ago |
| verilog-pcie Interfaces and peripherals | M2 · Simulation-tested | MIT | — | updated 2 years ago |
| IObundle Ethernet Interfaces and peripherals | M4 · Production-ready | CERN-OHL-S-2.0 | — | updated 11 days ago |
| Orthogone ULL PCIe circular-buffer DMA controller (Gen3/Gen4) Interfaces and peripherals | M1 · Prototype | Commercial license; encrypted RTL (closed source) | Verilog | — |
| Orthogone ULL 10G TCP/IP and UDP/IP Offload Engine Interfaces and peripherals | M1 · Prototype | Commercial license; encrypted RTL (closed source) | Verilog | — |
| Orthogone ULL Ethernet MAC/PCS 1G-100G with optional RS-FEC Interfaces and peripherals | M1 · Prototype | Commercial license; encrypted RTL (closed source) | Verilog | — |
| IObundle UART16550 Interfaces and peripherals | M4 · Production-ready | No license found | — | updated 11 days ago |
| LiteEth Interfaces and peripherals | M2 · Simulation-tested | No license found | Migen/Python/Verilog | updated 4 days ago |
| LiteICLink Interfaces and peripherals | M2 · Simulation-tested | No license found | — | updated 4 days ago |
| LitePCIe Interfaces and peripherals | M2 · Simulation-tested | No license found | Migen/Python/Verilog | updated 8 days ago |
| verilog-spi Interfaces and peripherals | M1 · Prototype | No license found | — | — |
| opencores pwm Interfaces and peripherals | M1 · Prototype | No license found | Verilog/VHDL unknown until review | — |
| opencores simple spi Interfaces and peripherals | M1 · Prototype | No license found | Verilog/VHDL unknown until review | — |
| OpenCores UART16550 Interfaces and peripherals | M1 · Prototype | No license found | Verilog | — |
| OpenCores Ethernet MAC Interfaces and peripherals | M1 · Prototype | No license found | Verilog | — |
| OpenCores I2C controller Interfaces and peripherals | M1 · Prototype | No license found | Verilog | — |
| OpenCores SPI master/slave Interfaces and peripherals | M1 · Prototype | No license found | Verilog | — |
| opencores can core Interfaces and peripherals | M1 · Prototype | No license found | Verilog/VHDL unknown until review | — |