Cores
Open HDL cores for FPGA. License, tests and activity checked on GitHub.
| Core | Maturity | License | Language | Activity |
|---|---|---|---|---|
| Project F FPGA graphics Educational | M2 · Simulation-tested | MIT | — | updated 8 months ago |
| AccelFury core-template Generators and frameworks | M2 · Simulation-tested | CERN-OHL-S-2.0 + AGPL + CC-BY-SA | Rust/SystemVerilog/TypeScript | updated 5 months ago |
| Project F display controller Audio and video | M2 · Simulation-tested | MIT | — | updated 8 months ago |
| verilog-i2c Interfaces and peripherals | M2 · Simulation-tested | MIT | — | updated 2 years ago |
| ultraembedded riscv CPUs and compute | M2 · Simulation-tested | BSD-3-Clause | — | updated 5 years ago |
| verilog-pcie Interfaces and peripherals | M2 · Simulation-tested | MIT | — | updated 2 years ago |
| BOOM CPUs and compute | M1 · Prototype | BSD-3-Clause | — | updated 21 days ago |
| IObundle Ethernet Interfaces and peripherals | M4 · Production-ready | CERN-OHL-S-2.0 | — | updated 11 days ago |
| taxi Buses and infrastructure | M2 · Simulation-tested | CERN-OHL-S-2.0 | — | updated 35 days ago |
| OpenHW CORE-V cores CPUs and compute | M1 · Prototype | Solderpad | SystemVerilog | updated 6 months ago |
| LiteX Generators and frameworks | M4 · Production-ready | M6 | Migen/Python/Verilog | updated 8 days ago |
| jotego JT12 Audio and video | M2 · Simulation-tested | GPL-3.0 | Verilog | updated 31 days ago |
| jt51 Audio and video | M2 · Simulation-tested | GPL-3.0 | — | updated 2 months ago |
| jtopl Audio and video | M2 · Simulation-tested | GPL-3.0 | — | updated 2 months ago |
| colibri Buses and infrastructure | M1 · Prototype | CERN-OHL-W-2.0 | VHDL-2008 | — |
| IObundle cache Memory and storage | M1 · Prototype | CERN-OHL-S-2.0 | — | updated 11 days ago |
| Orthogone ULL PCIe circular-buffer DMA controller (Gen3/Gen4) Interfaces and peripherals | M1 · Prototype | Commercial license; encrypted RTL (closed source) | Verilog | — |
| Orthogone ULL 10G TCP/IP and UDP/IP Offload Engine Interfaces and peripherals | M1 · Prototype | Commercial license; encrypted RTL (closed source) | Verilog | — |
| Orthogone ULL Ethernet MAC/PCS 1G-100G with optional RS-FEC Interfaces and peripherals | M1 · Prototype | Commercial license; encrypted RTL (closed source) | Verilog | — |
| jotego jtcores Retro | M2 · Simulation-tested | GPL-3.0 | Verilog | updated 4 days ago |
| OpenHW CVA6 CPUs and compute | M4 · Production-ready | No license found | SystemVerilog | updated 4 days ago |
| pulp-platform common_cells Buses and infrastructure | M4 · Production-ready | No license found | SystemVerilog | updated 14 days ago |
| OpenHW CV32E40P CPUs and compute | M4 · Production-ready | No license found | SystemVerilog | updated 1 day ago |
| ultraembedded core_soc CPUs and compute | M1 · Prototype | GPL-2.0 | — | updated 6 years ago |