Cores

Open HDL cores for FPGA. License, tests and activity checked on GitHub.

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106 results · Page 2 of 5

Cards Table

Project F FPGA graphics

Checked on GitHub

Good KB reference for graphics pipelines.

EducationalMITM2 · Simulation-testedupdated 8 months ago

AccelFury core-template

Checked on GitHub

FPGA IP template with a manifest, board and toolchain configuration, SPDX checks, separate licenses and a release checklist.

Generators and frameworksRust/SystemVerilog/TypeScriptCERN-OHL-S-2.0 + AGPL + CC-BY-SAM2 · Simulation-testedupdated 5 months ago

Project F display controller

Checked on GitHub

Clear video/display learning resource.

Audio and videoMITM2 · Simulation-testedupdated 8 months ago

verilog-i2c

Checked on GitHub

I2C core alternative.

Interfaces and peripheralsMITM2 · Simulation-testedupdated 2 years ago

ultraembedded riscv

Checked on GitHub

RISC-V core comparison source.

CPUs and computeBSD-3-ClauseM2 · Simulation-testedupdated 5 years ago

verilog-pcie

Checked on GitHub

PCIe endpoint/DMA candidate.

Interfaces and peripheralsMITM2 · Simulation-testedupdated 2 years ago

BOOM

Checked on GitHub

High-end RISC-V research core.

CPUs and computeBSD-3-ClauseM1 · Prototypeupdated 21 days ago

IObundle Ethernet

Checked on GitHub

Ethernet candidate with OpenCores ethmac relation.

Interfaces and peripheralsCERN-OHL-S-2.0M4 · Production-readyupdated 11 days ago

taxi

Checked on GitHub

Successor ecosystem for AXI/stream components.

Buses and infrastructureCERN-OHL-S-2.0M2 · Simulation-testedupdated 34 days ago

OpenHW CORE-V cores

Checked on GitHub

Open RISC-V processor cores.

CPUs and computeSystemVerilogSolderpadM1 · Prototypeupdated 6 months ago

LiteX

Checked on GitHub

Central open SoC builder and integration framework.

Generators and frameworksMigen/Python/VerilogCustom licenseM4 · Production-readyupdated 8 days ago

jotego JT12

Checked on GitHub

FM sound core useful for retro/audio category.

Audio and videoVerilogGPL-3.0M2 · Simulation-testedupdated 31 days ago

jt51

Checked on GitHub

YM2151 clone candidate.

Audio and videoGPL-3.0M2 · Simulation-testedupdated 2 months ago

jtopl

Checked on GitHub

OPL-compatible sound core candidate.

Audio and videoGPL-3.0M2 · Simulation-testedupdated 2 months ago

colibri

CERN's library of common RTL components in VHDL-2008: memories, I/O, clock domain crossing, stream interfaces. Licence CERN-OHL-W-2.0.

Buses and infrastructureVHDL-2008CERN-OHL-W-2.0M1 · Prototype

IObundle cache

Checked on GitHub

Open cache candidate.

Memory and storageCERN-OHL-S-2.0M1 · Prototypeupdated 11 days ago

Orthogone ULL PCIe circular-buffer DMA controller (Gen3/Gen4)

Commercial PCIe DMA IP between FPGA and host with kernel-bypass Linux driver; encrypted RTL, commercial license.

Interfaces and peripheralsVerilogCustom licenseM1 · Prototype

Orthogone ULL 10G TCP/IP and UDP/IP Offload Engine

Commercial 10G TCP/IP and UDP/IP offload engine IP (L2-L4) with AXI-4 Stream interfaces; encrypted RTL, commercial license.

Interfaces and peripheralsVerilogCustom licenseM1 · Prototype

Orthogone ULL Ethernet MAC/PCS 1G-100G with optional RS-FEC

Commercial Ethernet MAC/PCS IP for 1G to 100G with optional RS-FEC at 25G and 100G; encrypted RTL, commercial license.

Interfaces and peripheralsVerilogCustom licenseM1 · Prototype

jotego jtcores

Checked on GitHub

Large curated arcade FPGA core ecosystem.

RetroVerilogGPL-3.0M2 · Simulation-testedupdated 4 days ago

OpenHW CVA6

Checked on GitHub

Linux-capable RISC-V core lineage.

CPUs and computeSystemVerilogNo license foundM4 · Production-readyupdated 4 days ago

pulp-platform common_cells

Checked on GitHub

Reusable cells widely used by PULP projects.

Buses and infrastructureSystemVerilogNo license foundM4 · Production-readyupdated 14 days ago

OpenHW CV32E40P

Checked on GitHub

Specific CORE-V core with verification evidence.

CPUs and computeSystemVerilogNo license foundM4 · Production-readyupdated 1 day ago

ultraembedded core_soc

Checked on GitHub

SoC integration candidate.

CPUs and computeGPL-2.0M1 · Prototypeupdated 6 years ago