FPGA/ASIC/HDL/IP core catalog

Cores catalog

FPGA/ASIC/HDL/IP cores

An evidence-first catalog for fast engineering triage: reusable value, license risk, verification depth, and board fit before you open the upstream repo.

Submit a core

Cores124

P0 launch52

Needs review122

Open flow4

Board linked2

High-risk records in the current index

Submit evidence

P0confidence 2/5

OpenTitan IP blocks

High-quality IP block library with docs and verification culture.

Warning

Manual review is required.

P0confidence 2/5

Ibex

Small open RISC-V CPU used by OpenTitan.

Warning

Manual review is required.

P0confidence 2/5

LiteX

Central open SoC builder and integration framework.

Warning

Manual review is required.

P0confidence 2/5

OpenCores Wishbone

Bus protocol reference for OpenCores-era reusable IP.

Warning

Manual review is required.

P0confidence 2/5

OpenCores WBScope

Useful Wishbone-accessible debug core by ZipCPU author.

Warning

Manual review is required.

Catalog

82 records

Core	License / review	Interfaces / flow	Warnings
OpenTitan IP blockssecurity/root-of-trust/IP blocks P0Auto indexedgithub High-quality IP block library with docs and verification culture.	Apache-2.0Lower commercial riskM1-M3 candidate	SystemVerilogunknownunknownVerilator	Manual review is required.
Ibexprocessor/RISC-V P0Auto indexedgithub Small open RISC-V CPU used by OpenTitan.	Apache-2.0Lower commercial riskM7 candidate	SystemVerilogunknownunknownVerilator	Manual review is required.
LiteXSoC builder/generator P0Auto indexedgithub Central open SoC builder and integration framework.	BSD-2-Clause-like until checkedLower commercial riskM6	Migen/Python/VerilogMemoryunknownLiteX, Verilator	Manual review is required.
AccelFury core-templategenerator / template / IP methodology P2Manually reviewedgithub Шаблон production-style FPGA IP: manifest, registry, board/toolchain scaffolding, SPDX checks, separated licenses and release checklist.	CERN-OHL-S-2.0 + AGPL + CC-BY-SALicense needs reviewM2-M3 template	Rust/SystemVerilog/TypeScriptunknownunknownVerilator	This is a template/example, not a standalone core.Generated projects require separate review.
OpenHW CORE-V coresprocessor/RISC-V P0Auto indexedgithub Industrial-grade open RISC-V core family source.	SolderpadLicense needs reviewM1-M3 candidate	SystemVerilogunknownunknownVerilator	Manual review is required.
jotego jtcoresretro/arcade P0Auto indexedgithub Large curated arcade FPGA core ecosystem.	GPL-3.0License needs reviewM1-M3 candidate	VerilogunknownunknownVerilator	There is legal risk around ROM/retro assets.
AccelFury af-pdm-rxaudio / sensor interface / PDM RX P1Manually reviewedgithub Raw PDM RX core на Verilog-2001 для MEMS microphones: генерирует PDM clock, сэмплирует 1-битный поток и выдаёт valid/ready stream. Не выполняет PDM-to-PCM decimation.	AccelFury Source AvailableSource-available limitationM4-M5 candidate	Verilog-2001PDMunknownVerilator	Source is available, but commercial use may require a separate license.The core does not include a decimator/CIC/FIR pipeline.Confirmed board evidence with a real microphone is still missing.
SERVprocessor/RISC-V/tiny P0Auto indexedgithub Tiny RISC-V core and FuseSoC-friendly ecosystem.	unknownNo clear licenseM1-M3 candidate	VerilogunknownunknownFuseSoC, Verilator	The license requires manual review.
OpenHW CV32E40Pprocessor/RISC-V P1Unreviewedgithub Specific CORE-V core with verification evidence.	unknownNo clear licenseunknown	SystemVerilogunknownunknownVerilator	The license requires manual review.
CORE-V-VERIFverification/RISC-V P0Auto indexedgithub Verification evidence model for CORE-V cores.	unknownNo clear licenseM1-M3 candidate	SystemVerilog/UVMunknownunknownVerilator	The license requires manual review.
Open Logic AXI/base/intflibrary/interfaces/math P0Auto indexedgithub FuseSoC-listed open logic package family.	unknownNo clear licenseM1-M3 candidate	unknownunknownAXIFuseSoC	The license requires manual review.
ZipCPUprocessor/soft CPU P0Auto indexedgithub CPU, Wishbone and formal-heavy ecosystem.	unknownNo clear licenseM1-M3 candidate	VerilogunknownWishboneVerilator	The license requires manual review.
ZipCPU wb2axipbus bridge/formal P0Auto indexedgithub Wishbone/AXI bridge and formal property library.	unknownNo clear licenseM1-M3 candidate	VerilogunknownWishbone, AXIVerilator	The license requires manual review.
LiteDRAMmemory/DRAM P0Auto indexedgithub Open DRAM controller ecosystem used with LiteX.	unknownNo clear licenseM1-M3 candidate	Migen/Python/VerilogMemoryunknownLiteX, Verilator	The license requires manual review.
VexRiscvprocessor/RISC-V/generator P0Auto indexedgithub Configurable RISC-V softcore used in LiteX ecosystem.	unknownNo clear licenseM1-M3 candidate	SpinalHDL/Scala/VerilogunknownunknownLiteX, Verilator	The license requires manual review.
wb_bfmverification/Wishbone BFM P0Auto indexedgithub Verification helper for Wishbone cores.	unknownNo clear licenseM1-M3 candidate	unknownunknownWishboneunknown	The license requires manual review.
LiteSATAstorage/SATA P0Auto indexedgithub High-value storage/networked design reference.	unknownNo clear licenseM1-M3 candidate	Migen/Python/VerilogSATAunknownLiteX, Verilator	The license requires manual review.
LiteSPIperipheral/SPI flash P0Auto indexedgithub Common SPI/SPI flash block in LiteX designs.	unknownNo clear licenseM1-M3 candidate	Migen/Python/VerilogSPI/QSPIunknownLiteX, Verilator	The license requires manual review.
YosysHQ sbyformal/tooling P0Auto indexedgithub Formal verification flow signal.	unknownNo clear licenseM0-M2	unknownunknownunknownYosys	The license requires manual review.This is not confirmed to be a reusable RTL core.
Amaranth HDLgenerator/Amaranth P0Auto indexedgithub Modern Python-based HDL ecosystem source.	unknownNo clear licenseM1-M3 candidate	unknownunknownunknownunknown	The license requires manual review.
LiteEthnetwork/Ethernet P0Auto indexedgithub Modern Ethernet core comparison point.	unknownNo clear licenseM1-M3 candidate	Migen/Python/VerilogEthernetunknownLiteX, Verilator	The license requires manual review.
NEORV32processor/RISC-V/SoC P0Auto indexedgithub Well-documented VHDL RISC-V SoC candidate.	unknownNo clear licenseM1-M3 candidate	VHDLunknownunknownGHDL	The license requires manual review.
PicoRV32processor/RISC-V P0Auto indexedgithub Compact softcore with strong FPGA relevance.	unknownNo clear licenseM1-M3 candidate	VerilogunknownunknownVerilator	The license requires manual review.
pulp-platform axibus/AXI P0Auto indexedgithub AXI components and infrastructure.	unknownNo clear licenseM1-M3 candidate	SystemVerilogunknownAXIVerilator	The license requires manual review.
pulp-platform common_cellslibrary/SystemVerilog cells P0Auto indexedgithub Reusable cells widely used by PULP projects.	unknownNo clear licenseM1-M3 candidate	SystemVerilogunknownunknownVerilator	The license requires manual review.
pulp-platform cva6processor/RISC-V P0Auto indexedgithub Linux-capable RISC-V core lineage.	unknownNo clear licenseM1-M3 candidate	SystemVerilogunknownunknownVerilator	The license requires manual review.
wb_interconbus/Wishbone interconnect P0Auto indexedgithub Common Wishbone interconnect package.	unknownNo clear licenseM1-M3 candidate	unknownunknownWishboneunknown	The license requires manual review.
fifomemory/FIFO P0Auto indexedgithub Generic FIFO baseline.	unknownNo clear licenseM1-M3 candidate	unknownFIFO/stream, Memoryunknownunknown	The license requires manual review.
IObundle UART16550peripheral/UART P0Auto indexedgithub Modern adaptation of OpenCores UART16550.	unknownNo clear licenseM1-M3 candidate	unknownUARTunknownunknown	The license requires manual review.
uart verilog by alexforencichperipheral/UART P0Auto indexedgithub Common GitHub UART implementation.	unknownNo clear licenseM1-M3 candidate	unknownUARTunknownVerilator	The license requires manual review.
cdc_utilsCDC utilities P0Auto indexedgithub CDC helpers for composition planner.	unknownNo clear licenseM1-M3 candidate	unknownunknownunknownunknown	The license requires manual review.
IObundle cachememory/cache P0Auto indexedgithub Open cache candidate.	unknownNo clear licenseM1-M3 candidate	unknownMemoryunknownunknown	The license requires manual review.
IObundle Ethernetnetwork/Ethernet P0Auto indexedgithub Ethernet candidate with OpenCores ethmac relation.	unknownNo clear licenseM1-M3 candidate	unknownEthernetunknownunknown	The license requires manual review.
jotego JT12audio/FM synthesis P0Auto indexedgithub FM sound core useful for retro/audio category.	unknownNo clear licenseM1-M3 candidate	VerilogunknownunknownVerilator	The license requires manual review.
LiteScopedebug/logic analyzer P0Auto indexedgithub Debug infrastructure for composition planner.	unknownNo clear licenseM1-M3 candidate	Migen/Python/VerilogJTAG/debugunknownLiteX, Verilator	The license requires manual review.
LiteSDCardstorage/SDCard P0Auto indexedgithub Useful storage peripheral for SoC designs.	unknownNo clear licenseM1-M3 candidate	Migen/Python/VerilogSD/SDIOunknownLiteX, Verilator	The license requires manual review.
stream_utilsstream utilities P0Auto indexedgithub Stream FIFO/width conversion baseline.	unknownNo clear licenseM1-M3 candidate	unknownFIFO/streamunknownunknown	The license requires manual review.
Wally RISC-Vprocessor/RISC-V P0Auto indexedgithub Open RISC-V core family for comparison.	unknownNo clear licenseM1-M3 candidate	SystemVerilogunknownunknownVerilator	The license requires manual review.
wb_rammemory/Wishbone RAM P0Auto indexedgithub Minimal SoC building block.	unknownNo clear licenseM1-M3 candidate	unknownMemoryWishboneunknown	The license requires manual review.
Project F FPGA graphicsvideo/education P1Unreviewedgithub Good KB reference for graphics pipelines.	unknownNo clear licenseunknown	unknownunknownunknownunknown	The license requires manual review.
OpenRISC or1200processor/OpenRISC P0Auto indexedgithub Historical open soft CPU baseline.	unknownNo clear licenseM1-M3 candidate	VerilogunknownunknownVerilator	The license requires manual review.Manual review is required.
LitePCIeperipheral/PCIe P0Auto indexedgithub Open PCIe ecosystem core.	unknownNo clear licenseM1-M3 candidate	Migen/Python/VerilogPCIeunknownLiteX, Verilator	The license requires manual review.There is a vendor tooling or license constraint.
LambdaConcept LiteICLinkSerDes/inter-chip P1Unreviewedgithub LiteX complex link core.	unknownNo clear licenseunknown	unknownunknownunknownLiteX	The license requires manual review.
F4PGAtoolchain/open FPGA flow P1Unreviewedgithub Open flow support signal.	unknownNo clear licenseunknown	unknownunknownunknownYosys	The license requires manual review.
Caliptra RTLsecurity/root-of-trust P1Unreviewedgithub CHIPS Alliance root-of-trust IP.	unknownNo clear licenseunknown	unknownunknownunknownunknown	The license requires manual review.
Rocket Chipprocessor/RISC-V/generator P1Unreviewedgithub Important Chisel generator ecosystem.	unknownNo clear licenseunknown	unknownunknownunknownunknown	The license requires manual review.
verilog-axibus/AXI P1Unreviewedgithub AXI component library and comparison source.	unknownNo clear licenseunknown	unknownunknownAXIVerilator	The license requires manual review.
verilog-ethernetnetwork/Ethernet P1Unreviewedgithub Ethernet MAC/UDP/IP stack candidate.	unknownNo clear licenseunknown	unknownEthernetunknownVerilator	The license requires manual review.
YosysHQ nextpnrtoolchain/place-and-route P0Auto indexedgithub Open P&R support signal.	unknownNo clear licenseM0-M2	unknownunknownunknownYosys, nextpnr	The license requires manual review.This is not confirmed to be a reusable RTL core.
YosysHQ yosystoolchain/synthesis P0Auto indexedgithub Open synthesis toolchain for support matrix.	unknownNo clear licenseM0-M2	unknownunknownunknownYosys	The license requires manual review.This is not confirmed to be a reusable RTL core.
Amaranth stdlibgenerator/stdlib P1Unreviewedgithub Amaranth ecosystem discovery root.	unknownNo clear licenseunknown	unknownunknownunknownunknown	The license requires manual review.
BaseJump STLlibrary/SystemVerilog P1Unreviewedgithub Reusable SystemVerilog library.	unknownNo clear licenseunknown	unknownunknownunknownVerilator	The license requires manual review.
Berkeley HardFloatmath/floating point P1Unreviewedgithub Floating-point arithmetic core family.	unknownNo clear licenseunknown	unknownunknownunknownunknown	The license requires manual review.
BlackParrotprocessor/RISC-V manycore P1Unreviewedgithub Manycore RISC-V candidate.	unknownNo clear licenseunknown	unknownunknownunknownunknown	The license requires manual review.
BOOMprocessor/RISC-V OoO P1Unreviewedgithub High-end RISC-V research core.	unknownNo clear licenseunknown	unknownunknownunknownunknown	The license requires manual review.
hdl-util VGAvideo/VGA P1Unreviewedgithub VGA timing core candidate.	unknownNo clear licenseunknown	unknownVGA/HDMIunknownunknown	The license requires manual review.
jt51audio/FM synthesis P1Unreviewedgithub YM2151 clone candidate.	unknownNo clear licenseunknown	unknownunknownunknownunknown	The license requires manual review.
jtoplaudio/FM synthesis P1Unreviewedgithub OPL-compatible sound core candidate.	unknownNo clear licenseunknown	unknownunknownunknownunknown	The license requires manual review.
LiteHyperBusmemory/HyperBus P1Unreviewedgithub HyperRAM/HyperFlash ecosystem core.	unknownNo clear licenseunknown	unknownMemoryunknownunknown	The license requires manual review.
LiteJESD204Bconverter/JESD204B P1Unreviewedgithub JESD204B open core candidate.	unknownNo clear licenseunknown	unknownunknownunknownunknown	The license requires manual review.
OpenHW CV32E40Sprocessor/RISC-V/security P1Unreviewedgithub Security-oriented CORE-V core variant.	unknownNo clear licenseunknown	unknownunknownunknownunknown	The license requires manual review.
OpenHW CV32E40Xprocessor/RISC-V P1Unreviewedgithub CORE-V core variant.	unknownNo clear licenseunknown	unknownunknownunknownunknown	The license requires manual review.
Project F display controllervideo/display P1Unreviewedgithub Clear video/display learning resource.	unknownNo clear licenseunknown	unknownVGA/HDMIunknownunknown	The license requires manual review.
taxibus/AXI/stream P1Unreviewedgithub Successor ecosystem for AXI/stream components.	unknownNo clear licenseunknown	unknownFIFO/streamAXIunknown	The license requires manual review.
ultraembedded core_socSoC/RISC-V P1Unreviewedgithub SoC integration candidate.	unknownNo clear licenseunknown	unknownunknownunknownunknown	The license requires manual review.
ultraembedded riscvprocessor/RISC-V P1Unreviewedgithub RISC-V core comparison source.	unknownNo clear licenseunknown	unknownunknownunknownunknown	The license requires manual review.
verilog-i2cperipheral/I2C P1Unreviewedgithub I2C core alternative.	unknownNo clear licenseunknown	unknownI2CunknownVerilator	The license requires manual review.
verilog-spiperipheral/SPI P1Unreviewedgithub SPI core alternative.	unknownNo clear licenseunknown	unknownSPI/QSPIunknownVerilator	The license requires manual review.
OpenRISC mor1kxprocessor/OpenRISC P0Auto indexedgithub OpenRISC core relevant to Wishbone history.	unknownNo clear licenseM1-M3 candidate	VerilogunknownWishboneVerilator	The license requires manual review.The source appears stale or legacy.
verilog-pcieperipheral/PCIe P1Unreviewedgithub PCIe endpoint/DMA candidate.	unknownNo clear licenseunknown	unknownPCIeunknownVerilator	The license requires manual review.There is a vendor tooling or license constraint.
MiSTer-devel organizationretro/platform P0Auto indexedgithub Central MiSTer ecosystem source.	unknownNo clear licenseM1-M3 candidate	unknownunknownunknownunknown	The license requires manual review.There is legal risk around ROM/retro assets.
hdl-util HDMIvideo/HDMI P1Unreviewedgithub Open HDMI/DVI transmitter candidate.	unknownNo clear licenseunknown	Verilog/VHDLVGA/HDMIunknownVerilator, GHDL	The license requires manual review.There is a vendor tooling or license constraint.
verilog-axisbus/AXI-Stream P1Unreviewedgithub AXI-Stream component library.	unknownNo clear licenseunknown	unknownFIFO/streamAXIVerilator	The license requires manual review.
Veribletooling/lint/format P1Unreviewedgithub Lint/style evidence tool.	unknownNo clear licenseM0-M2	unknownunknownunknownunknown	The license requires manual review.This is not confirmed to be a reusable RTL core.
FPGA Interchangetooling/interchange P1Unreviewedgithub Toolchain interoperability source.	unknownNo clear licenseM0-M2	unknownunknownunknownunknown	The license requires manual review.This is not confirmed to be a reusable RTL core.
Surelogtooling/SystemVerilog parser P1Unreviewedgithub SystemVerilog parsing support signal.	unknownNo clear licenseM0-M2	unknownunknownunknownVerilator	The license requires manual review.This is not confirmed to be a reusable RTL core.
UHDMtooling/SystemVerilog data model P1Unreviewedgithub SV tooling ecosystem source.	unknownNo clear licenseM0-M2	unknownunknownunknownVerilator	The license requires manual review.This is not confirmed to be a reusable RTL core.
MiSTer ao486retro/computer/x86 P1Unreviewedgithub Complex retro computer core.	unknownNo clear licenseunknown	unknownunknownunknownunknown	The license requires manual review.There is legal risk around ROM/retro assets.
MiSTer Minimigretro/computer P1Unreviewedgithub Computer core example for retro taxonomy.	unknownNo clear licenseunknown	unknownunknownunknownunknown	The license requires manual review.There is legal risk around ROM/retro assets.
MiSTer NESretro/console P1Unreviewedgithub Console core example.	unknownNo clear licenseunknown	unknownunknownunknownunknown	The license requires manual review.There is legal risk around ROM/retro assets.
MiSTer SNESretro/console P1Unreviewedgithub Console core example.	unknownNo clear licenseunknown	unknownunknownunknownunknown	The license requires manual review.There is legal risk around ROM/retro assets.
MiSTer Main_MiSTerretro/platform P1Unreviewedgithub MiSTer platform integration source.	unknownNo clear licenseunknown	unknownunknownunknownunknown	The license requires manual review.There is legal risk around ROM/retro assets.