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edu.fpga.camp

FPGA Challenges

Verifiable FPGA challenges for HDL, simulation, constraints, timing, CDC, and EDA tools. Execution is local; fpga.camp validates only a safe report.json.

Find the right task

Start with the toolchain and time budget. Open the task when you know what to run; use report validation when you already have report.json.

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Showing 4 of 4 public challenges.Add a challenge
Public challenges4
Published3
Local checker4
Tracks4

Workflow

  1. 1. Choose a task by track, difficulty, toolchain, or estimated time.
  2. 2. Download the task package and run the checker locally.
  3. 3. Upload only the generated report.json, maximum 512 KB.
  4. 4. Review score, failed checks, warnings, and the next fix to make.
D1: 1D2: 1D3: 2D4: 0D5: 0iverilog: 2verilator: 3yosys: 1nextpnr: 1symbiyosys: 1vivado: 1
HDL basics: 1Simulation: 1Timing: 1CDC: 1
D1HDL basicsCC-BY-4.0OriginalLocal checkerPublished

Counter with enable and reset

A basic HDL task: implement a parameterized counter and verify reset, enable, and rollover in local simulation.

Time
25-45 min
Pass score
80/100
HDL
Verilog
Audience
Beginner, Student, Junior engineer
Package
Download available
Next step
Run locally, upload report.json
iverilogverilator
OpenDownload
D2SimulationCC-BY-4.0OriginalLocal checkerPublished

FIFO and simulation scoreboard

A local FIFO simulation task: verify data order, full/empty behavior, and no reads from an empty queue.

Time
45-90 min
Pass score
75/100
HDL
SystemVerilog
Audience
Student, Junior engineer, Engineer
Package
Download available
Next step
Run locally, upload report.json
iverilogverilator
OpenDownload
D3CDCCC-BY-4.0OriginalLocal checkerPublished

Two-flop CDC synchronizer

A CDC task: implement a safe 2FF synchronizer, check reset assumptions, and record proof limitations.

Time
50-110 min
Pass score
80/100
HDL
SystemVerilog
Audience
Junior engineer, Engineer, Maintainer
Package
Download available
Next step
Run locally, upload report.json
verilatorsymbiyosys
OpenDownload
D3TimingCC-BY-4.0OriginalLocal checkerIn review

Clock constraint and timing summary

A constraints task: define a clock, run a local timing flow, and interpret pass/fail without uploading vendor logs.

Time
60-120 min
Pass score
70/100
HDL
Verilog
Audience
Junior engineer, Engineer, Teacher
Package
Download available
Next step
Run locally, upload report.json
yosysnextpnrvivado
OpenDownload