Sign in
edu.fpga.camp

Constraints & Timing Trainer

Mini XDC/SDC checks, setup/hold/slack quizzes and CDC basics. No timing or CDC signoff claims.

Create primary clock

constraints_checkD2

Implement the requested behavior in a small bounded mixed module. The platform controls the testbench and command profile.

Wrong port name

constraints_checkD2

Implement the requested behavior in a small bounded mixed module. The platform controls the testbench and command profile.

Missing clock

constraints_checkD3

Implement the requested behavior in a small bounded mixed module. The platform controls the testbench and command profile.

Generated clock explanation

constraints_checkD4

Implement the requested behavior in a small bounded mixed module. The platform controls the testbench and command profile.

IO pin mismatch

constraints_checkD3

Implement the requested behavior in a small bounded mixed module. The platform controls the testbench and command profile.

IO standard mismatch

constraints_checkD3

Implement the requested behavior in a small bounded mixed module. The platform controls the testbench and command profile.

Setup slack

timing_reportD3

Implement the requested behavior in a small bounded mixed module. The platform controls the testbench and command profile.

Hold slack

timing_reportD3

Implement the requested behavior in a small bounded mixed module. The platform controls the testbench and command profile.

False path concept

timing_reportD4

Implement the requested behavior in a small bounded mixed module. The platform controls the testbench and command profile.

Multicycle path concept

timing_reportD5

Implement the requested behavior in a small bounded mixed module. The platform controls the testbench and command profile.

CDC basics

timing_reportD4

Implement the requested behavior in a small bounded mixed module. The platform controls the testbench and command profile.

Match HDL ports to constraints

constraints_checkD2

Implement the requested behavior in a small bounded mixed module. The platform controls the testbench and command profile.

Critical path in adder chain

timing_reportD3

Implement the requested behavior in a small bounded mixed module. The platform controls the testbench and command profile.

Setup vs hold violation

timing_reportD3

Implement the requested behavior in a small bounded mixed module. The platform controls the testbench and command profile.

WNS/TNS basics

timing_reportD3

Implement the requested behavior in a small bounded mixed module. The platform controls the testbench and command profile.