Can apply fpga mental model in small FPGA exercises.
Recognizes the practical boundary of fpga mental model.
Can apply parallel hardware in small FPGA exercises.
Recognizes the practical boundary of parallel hardware.
Can apply combinational hdl in small FPGA exercises.
Recognizes the practical boundary of combinational hdl.
Can apply sequential hdl in small FPGA exercises.
Recognizes the practical boundary of sequential hdl.
Bit widths and signedness
Can apply bit widths and signedness in small FPGA exercises.
Recognizes the practical boundary of bit widths and signedness.
Can apply testbench basics in small FPGA exercises.
Recognizes the practical boundary of testbench basics.
Can apply waveform reading in small FPGA exercises.
Recognizes the practical boundary of waveform reading.
Can apply eda log triage in small FPGA exercises.
Recognizes the practical boundary of eda log triage.
Can apply clock constraints in small FPGA exercises.
Recognizes the practical boundary of clock constraints.
Can apply pin constraints in small FPGA exercises.
Recognizes the practical boundary of pin constraints.
Can apply timing basics in small FPGA exercises.
Recognizes the practical boundary of timing basics.
Can apply cdc basics in small FPGA exercises.
Recognizes the practical boundary of cdc basics.
Can apply board bring-up in small FPGA exercises.
Recognizes the practical boundary of board bring-up.
Can apply project integration in small FPGA exercises.
Recognizes the practical boundary of project integration.