Verilog continuous assign
verilogicarusD1
Practice: Verilog continuous assign.
edu.fpga.camp
HDL Practice Lab
Small bounded HDL tasks with platform-controlled testbenches and command profiles.
Verilog 2:1 mux
verilogicarusD1
Practice: Verilog 2:1 mux.
Verilog demux
verilogicarusD1
Practice: Verilog demux.
Verilog full adder
verilogicarusD1
Practice: Verilog full adder.
Verilog comparator
verilogicarusD2
Practice: Verilog comparator.
Verilog register
verilogicarusD2
Practice: Verilog register.
Verilog counter with enable
verilogicarusD2
Practice: Verilog counter with enable.
Verilog shift register
verilogicarusD2
Practice: Verilog shift register.
Verilog edge detector
verilogicarusD2
Practice: Verilog edge detector.
Verilog debounce
verilogicarusD3
Practice: Verilog debounce.
Verilog PWM generator
verilogicarusD3
Practice: Verilog PWM generator.
Verilog FSM traffic light
verilogicarusD3
Practice: Verilog FSM traffic light.
UART TX fragment
verilogicarusD4
Practice: UART TX fragment.
SPI fragment
verilogicarusD4
Practice: SPI fragment.
Simple FIFO basics
verilogicarusD4
Practice: Simple FIFO basics.
Avoid inferred latch
verilogverilatorD3
Practice: Avoid inferred latch.
Width-safe adder
verilogverilatorD3
Practice: Width-safe adder.
Signed comparator
verilogicarusD3
Practice: Signed comparator.
Ready/valid pass-through
verilogicarusD3
Practice: Ready/valid pass-through.
Minimal testbench clock/reset
verilogicarusD3
Practice: Minimal testbench clock/reset.
VHDL entity assignment
vhdlghdlD1
Practice: VHDL entity assignment.
VHDL 2:1 mux
vhdlghdlD1
Practice: VHDL 2:1 mux.
VHDL counter
vhdlghdlD2
Practice: VHDL counter.
VHDL synchronous reset
vhdlghdlD2
Practice: VHDL synchronous reset.
VHDL FSM
vhdlghdlD3
Practice: VHDL FSM.
VHDL shift register
vhdlghdlD2
Practice: VHDL shift register.
VHDL numeric_std conversion
vhdlghdlD3
Practice: VHDL numeric_std conversion.
VHDL avoid latch
vhdlghdlD3
Practice: VHDL avoid latch.
VHDL single-port RAM model
vhdlghdlD4
Practice: VHDL single-port RAM model.
VHDL pulse generator
vhdlghdlD3
Practice: VHDL pulse generator.
SystemVerilog subset always_ff counter
systemverilog_subsetverilatorD3
Practice: SystemVerilog subset always_ff counter.
SystemVerilog subset always_comb default
systemverilog_subsetverilatorD3
Practice: SystemVerilog subset always_comb default.
SystemVerilog enum FSM subset
systemverilog_subsetverilatorD4
Practice: SystemVerilog enum FSM subset.
Fix unused signal warning
verilogverilatorD2
Practice: Fix unused signal warning.
Fix combinational loop
verilogyosysD4
Practice: Fix combinational loop.
Fix multiple drivers
verilogverilatorD3
Practice: Fix multiple drivers.
Fix legacy sensitivity bug
verilogicarusD2
Practice: Fix legacy sensitivity bug.
Fix accidental latch
verilogverilatorD3
Practice: Fix accidental latch.
Parameterized width bug fix
verilogverilatorD4
Practice: Parameterized width bug fix.
Waveform reading task
verilogicarusD2
Practice: Waveform reading task.