Icarus syntax error near token
icaruserrorconfidence 0.86
Syntax is invalid for the selected Verilog profile.
edu.fpga.camp
EDA Error Decoder Library
Searchable EDA error patterns with causes, fixes, MRE and related tasks.
Icarus unknown module type
icaruserrorconfidence 0.86
A referenced module is missing or the top name is wrong.
Icarus unable to bind wire/reg
icaruserrorconfidence 0.86
A signal name is misspelled or out of scope.
GHDL no declaration for signal
ghdlerrorconfidence 0.86
A VHDL object is not visible in this scope.
GHDL numeric_std type mismatch
ghdlerrorconfidence 0.86
Arithmetic mixes incompatible VHDL types.
GHDL multiple sources for signal
ghdlerrorconfidence 0.86
More than one process drives a signal.
Verilator WIDTH
verilatorwarningconfidence 0.86
Expression width does not match target width.
Verilator LATCH
verilatorerrorconfidence 0.86
Combinational block leaves an output unassigned.
Verilator UNOPTFLAT
verilatorerrorconfidence 0.86
The design may contain a combinational loop or hard-to-optimize feedback.
Verilator MULTIDRIVEN
verilatorerrorconfidence 0.86
A signal has multiple procedural/continuous drivers.
Verilator UNUSED
verilatorwarningconfidence 0.86
A declared signal is not used by meaningful logic.
Verilator PINMISSING
verilatorerrorconfidence 0.86
An instance port is not connected.
Yosys multiple conflicting drivers
yosyserrorconfidence 0.86
Synthesis sees more than one driver for a net.
Yosys inferred latch
yosyserrorconfidence 0.86
Synthesis inferred storage from incomplete combinational logic.
Yosys unsupported construct in profile
yosyserrorconfidence 0.86
The selected educational profile does not support this HDL construct.
Vivado inferred latch warning
vivadowarningconfidence 0.72
Vivado inferred a latch from incomplete combinational logic.
Vivado clock not found in constraint
vivadoerrorconfidence 0.72
The XDC query did not match a clock object or port.
Vivado unconstrained path
vivadoerrorconfidence 0.72
Timing analysis has paths without required clock/input constraints.
Quartus top-level entity undefined
quartuserrorconfidence 0.72
Quartus cannot find the selected top-level entity.
Quartus pin assignment missing
quartuserrorconfidence 0.72
Board IO pin assignment is missing or incomplete.
Gowin constraint object not found
gowinerrorconfidence 0.72
Constraint object name does not match HDL port or hierarchy.
SDC create_clock target empty
yosyserrorconfidence 0.86
The create_clock command matched no target.
XDC get_ports matches no objects
vivadoerrorconfidence 0.72
The XDC port name does not exist in the current top module.
Simulation X at output
icaruserrorconfidence 0.86
A signal is uninitialized, reset is missing, or a branch is incomplete.
openFPGALoader cable not found
openfpgaloadererrorconfidence 0.86
The programmer cable is missing, busy or lacks permissions.