FPGA vs MCU and first simulation
Lab 1rubricmarkdown-ready
Uses seeded tasks, deterministic validation and common failure criteria. Classroom mode in v1 is read-only.
edu.fpga.camp
Educator Toolkit
Read-only v1 educator resources: labs, rubrics, task collections and 4/8/12 week plans.
Combinational Verilog/VHDL
Lab 2rubricmarkdown-ready
Uses seeded tasks, deterministic validation and common failure criteria. Classroom mode in v1 is read-only.
Sequential logic and reset
Lab 3rubricmarkdown-ready
Uses seeded tasks, deterministic validation and common failure criteria. Classroom mode in v1 is read-only.
FSM laboratory
Lab 4rubricmarkdown-ready
Uses seeded tasks, deterministic validation and common failure criteria. Classroom mode in v1 is read-only.
Testbench basics
Lab 5rubricmarkdown-ready
Uses seeded tasks, deterministic validation and common failure criteria. Classroom mode in v1 is read-only.
Waveform reading class
Lab 6rubricmarkdown-ready
Uses seeded tasks, deterministic validation and common failure criteria. Classroom mode in v1 is read-only.
EDA error clinic
Lab 7rubricmarkdown-ready
Uses seeded tasks, deterministic validation and common failure criteria. Classroom mode in v1 is read-only.
Constraints first principles
Lab 8rubricmarkdown-ready
Uses seeded tasks, deterministic validation and common failure criteria. Classroom mode in v1 is read-only.
Timing report basics
Lab 9rubricmarkdown-ready
Uses seeded tasks, deterministic validation and common failure criteria. Classroom mode in v1 is read-only.
Board starter capstone
Lab 10rubricmarkdown-ready
Uses seeded tasks, deterministic validation and common failure criteria. Classroom mode in v1 is read-only.
4 week plan
fpga-startembedded-to-fpgaverilog-fundamentals
8 week plan
fpga-startembedded-to-fpgaverilog-fundamentalsvhdl-fundamentalssimulation-firstconstraints-timing-basics
12 week plan
fpga-startembedded-to-fpgaverilog-fundamentalsvhdl-fundamentalssimulation-firstconstraints-timing-basicsopen-source-fpga-floweducator-lab-path