edu.fpga.camp
Clock constraint and timing summary
A constraints task: define a clock, run a local timing flow, and interpret pass/fail without uploading vendor logs.
30-second task brief
- Required tools
- yosys, nextpnr, vivado
- What to download
- Challenge package
- What to run
- make report
- Success condition
- At least 70/100 and no blocking report errors.
Challenge parameters
D3TimingCC-BY-4.0yosysnextpnrvivado
- HDL languages
- Verilog
- Vendor family
- Lattice iCE40, Xilinx 7-Series
- Estimated time
- 60-120 min
- Score
- pass 70 / max 100
- Authors
- FPGA.camp
- Updated
- 2026-05-19
Learning outcomes
- Distinguish a clock constraint from a pin constraint.
- Reduce a timing verdict to a safe report.json.
- Keep vendor license data and local paths out of public reports.
Prerequisites
- Basic understanding of synchronous logic.
- A locally installed open-source or vendor timing flow.
Files
- challenge.yaml
- rtl/top.v
- constraints/top.xdc
- reports/example_timing_summary.txt
How to run
Open-source timing flow
make timing TOOLCHAIN=yosys-nextpnr
Vendor timing flow
make timing TOOLCHAIN=vivado
Normalize timing verdict into report.json
make report
Scoring rubric
| id | criterion | points | required | evidence_path |
|---|---|---|---|---|
| clock-defined | Clock constraint is defined explicitly | 30 | yes | checks.clock_defined |
| timing-verdict | Timing verdict is extracted correctly | 40 | yes | checks.timing_verdict |
| privacy | Report has no local paths or license data | 30 | yes | privacy |
Common mistakes
- Using the wrong units for the clock period.
- Copying a full timing log into the report.
- Leaving absolute working-directory paths in messages.
Challenge package
- version
- 1.0.0
- size
- 318 bytes
- sha256
- ba153e6af726953ab7aaeb0beb5a4deefced7d0366382a5c1433a4863c241ffe
Validate report.json
Upload the report produced by the local runner. The server validates only normalized JSON and never runs HDL, Tcl, shell scripts, or EDA tools.
- Accepted: one
report.jsonfile, maximum 512 KB. - Rejected: HDL, Tcl, zip archives, waveforms, full logs, absolute paths, and embedded source code.