edu.fpga.camp
Counter with enable and reset
A basic HDL task: implement a parameterized counter and verify reset, enable, and rollover in local simulation.
30-second task brief
- Required tools
- iverilog, verilator
- What to download
- Challenge package
- What to run
- make check
- Success condition
- At least 80/100 and no blocking report errors.
Challenge parameters
D1HDL basicsCC-BY-4.0iverilogverilator
- HDL languages
- Verilog
- Vendor family
- Estimated time
- 25-45 min
- Score
- pass 80 / max 100
- Authors
- FPGA.camp
- Updated
- 2026-05-19
Learning outcomes
- Separate synchronous reset and enable behavior in sequential logic.
- Write a minimal testbench for counter boundary states.
- Read a local checker report.json without exposing HDL to the server.
Prerequisites
- Understanding of a clocked always block.
- Basic Verilog and local simulation workflow.
Files
- challenge.yaml
- rtl/counter.v
- tb/counter_tb.v
- checks/run.sh
How to run
Icarus Verilog simulation
make sim TOOL=iverilog
Verilator lint
make lint TOOL=verilator
Local check and report.json generation
make check
Scoring rubric
| id | criterion | points | required | evidence_path |
|---|---|---|---|---|
| reset-behavior | Reset drives the counter to zero | 30 | yes | checks.reset_behavior |
| enable-hold | The value is held when enable is 0 | 30 | yes | checks.enable_hold |
| rollover | Rollover matches the configured width | 40 | yes | checks.rollover |
Common mistakes
- Adding an asynchronous reset when the task requires a synchronous reset.
- Checking enable behavior for only one clock cycle.
- Ending the testbench before rollover is reached.
Challenge package
- version
- 1.0.0
- size
- 295 bytes
- sha256
- faf6c1ca5f3ac16e639b98a7768bb5b299aedb5b61fd3be413ee50618760612f
Validate report.json
Upload the report produced by the local runner. The server validates only normalized JSON and never runs HDL, Tcl, shell scripts, or EDA tools.
- Accepted: one
report.jsonfile, maximum 512 KB. - Rejected: HDL, Tcl, zip archives, waveforms, full logs, absolute paths, and embedded source code.