edu.fpga.camp
FIFO and simulation scoreboard
A local FIFO simulation task: verify data order, full/empty behavior, and no reads from an empty queue.
30-second task brief
- Required tools
- iverilog, verilator
- What to download
- Challenge package
- What to run
- make check
- Success condition
- At least 75/100 and no blocking report errors.
Challenge parameters
D2SimulationCC-BY-4.0iverilogverilator
- HDL languages
- SystemVerilog
- Vendor family
- Estimated time
- 45-90 min
- Score
- pass 75 / max 100
- Authors
- FPGA.camp
- Updated
- 2026-05-19
Learning outcomes
- Build a scoreboard without reading private DUT internals.
- Separate a functional pass from coverage-related warnings.
- Decide which messages are safe to include in report.json.
Prerequisites
- Basic valid/ready or write/read-enable handshake signals.
- Experience running an HDL testbench.
Files
- challenge.yaml
- rtl/fifo.sv
- tb/fifo_scoreboard_tb.sv
- checks/run.sh
How to run
SystemVerilog simulation
make sim
Scoreboard check and report.json generation
make check
Scoring rubric
| id | criterion | points | required | evidence_path |
|---|---|---|---|---|
| order | Data order is preserved | 35 | yes | checks.order |
| flags | full/empty flags are correct | 35 | yes | checks.flags |
| illegal-ops | Illegal reads and writes are detected | 30 | no | checks.illegal_ops |
Common mistakes
- Comparing scoreboard data before the handshake has completed.
- Checking full/empty only immediately after reset.
- Copying a long simulator log into report.json instead of a short verdict.
Challenge package
- version
- 1.0.0
- size
- 303 bytes
- sha256
- 05764311d13fe6a90dae295b7acf2cc712a823d655f1dbeb7ca329a2d36187ec
Validate report.json
Upload the report produced by the local runner. The server validates only normalized JSON and never runs HDL, Tcl, shell scripts, or EDA tools.
- Accepted: one
report.jsonfile, maximum 512 KB. - Rejected: HDL, Tcl, zip archives, waveforms, full logs, absolute paths, and embedded source code.