verilatorverilatorwarningconfidence 0.86
Remove it or connect intended logic.
// Minimal educational reproduction for Verilator UNUSED module top; endmodule
edu.fpga.camp
Verilator UNUSED
A declared signal is not used by meaningful logic.
A declared signal is not used by meaningful logic.
Remove it or connect intended logic.
// Minimal educational reproduction for Verilator UNUSED module top; endmodule