1. Interface and timing sketch
verilog-counter-enable
Explain clocks, reset and IO assumptions.
edu.fpga.camp
Audio/PDM or simple FIR
Build a staged Audio/PDM or simple FIR learning project with simulation and debug checkpoints.
2. Core HDL behavior
verilog-fsm-traffic-lightverilog-ready-valid-pass-through
Simulation passes deterministic tests.
3. Debug checklist and board variant
constraints-match-hdl-ports
Constraints are checked as educational examples, not signoff.
Completion criteria
All staged checks pass and final report lists limitations.
tang-nano-20kicebreaker-ice40arty-a7