Counter with enable and reset
A basic HDL task: implement a parameterized counter and verify reset, enable, and rollover in local simulation.
D1 · 25–45 min · iverilog, verilator
Local checker available
FPGA Challenges: HDL basics
Challenges to run locally.
How results are checked
Run this challenge on your computer. The site validates the structure of report.json. A submitted report alone does not prove that the task was completed.