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FPGA Challenges: HDL basics

Verifiable challenges in the HDL basics track. Execution is local; fpga.camp validates only report.json.

D1HDL basicsCC-BY-4.0OriginalLocal checkerPublished

Counter with enable and reset

A basic HDL task: implement a parameterized counter and verify reset, enable, and rollover in local simulation.

Time
25-45 min
Pass score
80/100
HDL
Verilog
Audience
Beginner, Student, Junior engineer
Package
Download available
Next step
Run locally, upload report.json
iverilogverilator
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