FIFO and simulation scoreboard
A local FIFO simulation task: verify data order, full/empty behavior, and no reads from an empty queue.
D2 · 45–90 min · iverilog, verilator
Local checker available
FPGA Challenges: Simulation
Challenges to run locally.
How results are checked
Run this challenge on your computer. The site validates the structure of report.json. A submitted report alone does not prove that the task was completed.