Clock constraint and timing summary
A constraints task: define a clock, run a local timing flow, and interpret pass/fail without uploading vendor logs.
D3 · 60–120 min · yosys, nextpnr, vivado
Local checker available
FPGA Challenges: Timing
Challenges to run locally.
How results are checked
Run this challenge on your computer. The site validates the structure of report.json. A submitted report alone does not prove that the task was completed.