verilatorverilatorerrorconfidence 0.86
Add default assignment or complete all branches.
// Minimal educational reproduction for Verilator LATCH module top; endmodule
edu.fpga.camp
Verilator LATCH
Combinational block leaves an output unassigned.
Combinational block leaves an output unassigned.
Add default assignment or complete all branches.
// Minimal educational reproduction for Verilator LATCH module top; endmodule