LiteJESD204B
Checked on GitHubJESD204B open core candidate.
DSP and radioNo license foundM2 · Simulation-testedupdated 8 days ago
Cores
Open HDL cores for FPGA. License, tests and activity checked on GitHub.
Example of DSP cores with Wishbone and claimed FPGA evidence.
DSP and radioVHDLLGPLM1 · Prototype
CORDIC category seed.
DSP and radioVerilog/VHDL unknown until reviewNo license foundM1 · Prototype
FFT category seed.
DSP and radioVerilog/VHDL unknown until reviewNo license foundM1 · Prototype